Despite the rapid development of semiconductor microelectronics technology and the increasing density of transistors on single-chip chips, the number of transistors on a single processor chip has increased from hundreds of millions to tens of billions. However, the cost per transistor on the chip has not decreased. Zvi Or-Bach, CEO of semiconductor integration company MonolithIC 3D, published an analysis report as early as 2014, showing that the cost per transistor stopped decreasing at 28nm. Recently, this finding was confirmed by Milind Shah. Google has also proven that since TSMC mass-produced 28nm planar process technology in 2012, the cost of 100 million gate transistors has increased.
Google’s findings show: “The cost expansion (0.7x) of transistors stalls at 28nm and remains flat with the same generation.”
For a long time, the industry has been worried that with the emergence of new nodes, the cost benefits per transistor will diminish. The latest chip manufacturing process technologies—such as 7nm, 5nm, and 3nm—require more complex wafer fab tools, costing up to hundreds of millions of dollars (such as ASML’s lithography machines up to $200 million), which has increased the cost of leading-edge wafer fabs from $20 billion to $30 billion. Of course, this makes the production cost on the leading-edge nodes very high. However, despite the increased complexity and cost of chip manufacturing over the years, it is of undeniable historical significance for technological development.
According to the chart presented by Google’s Milind Shah at the industry exhibition IEDM, the cost of 100 million standardized 28nm transistors is actually flat or even increasing. This lack of cost expansion reduces the attractiveness of some chip designs adopting some of the latest nodes. Moreover, it makes it more attractive to split some designs into chipsets, rather than producing single silicon chip designs using advanced nodes, to optimize cost and performance.
AMD’s Ryzen desktop CPU and Intel’s Meteor Lake laptop CPU are the most obvious examples of decentralized designs in the client computing domain, consisting of three or four small chips manufactured using different process technologies in different factories. In the data center domain, AMD’s epic success with its EPYC data center CPU is another example. Companies like AMD and Intel, worth billions, can carefully evaluate their design options and then use the best technology they have to manufacture products. For smaller manufacturers, things may not be so easy.
First, multi-chip designs tend to consume more power, so they are not the best choice for mobile devices. Second, multi-chip integration is a daunting engineering task, and companies like MonolithIC 3D that offer their multi-chip integration services (ultimately using advanced packaging technologies such as Intel’s Foveros or TSMC’s CoWoS) all require money. Third, advanced packaging technologies are expensive, and obtaining CoWoS allocation is difficult to get leading node allocation.
Therefore, new nodes may no longer make transistors cheaper.
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