01
What is Electrostatic Discharge (ESD)?
Let’s talk about Electrostatic Discharge (ESD): What is it? This is the primary culprit responsible for excessive electrical stress and damage to all electronic components or integrated circuit systems. Because static electricity often has an extremely high instantaneous voltage (> several thousand volts), this type of damage is destructive and permanent, leading to the direct burning of circuits. Therefore, preventing electrostatic damage is the top challenge in all IC design and manufacturing.
Static electricity is typically generated by human activities, such as production, assembly, testing, storage, and handling. Static electricity can accumulate in the human body, instruments, or equipment during these processes, and even the components themselves can accumulate static electricity. When people unknowingly come into contact with these charged objects, it forms a discharge path, instantly causing damage to electronic components or systems due to electrostatic discharge (which is why in the past, when repairing computers, it was necessary to wear anti-static wristbands and place them on the workbench to prevent electrostatic damage to the chips). It’s similar to the charge stored in clouds suddenly breaking through the cloud layer, creating intense lightning, and splitting the ground, usually occurring just before rain, because high humidity in the air easily forms a conductive path.
02
Let’s discuss how to prevent electrostatic discharge (ESD) damage
First and foremost, reducing static electricity at the source involves altering the environment (such as minimizing friction, avoiding woolen clothing, and controlling air temperature and humidity). However, this is not our focus today.
Today, we’re going to discuss how to protect circuits from ESD. When there’s external static electricity, our electronic components or systems need to be able to self-protect and avoid ESD damage (it’s essentially like installing a lightning rod). This is a major challenge for many IC designers and manufacturers, with many companies having dedicated ESD protection teams. Today, I’ll start with the most basic theory and gradually explain the principles and considerations for ESD protection. You’ll find that the concepts of PN junction/diodes, transistors, MOSFETs, and snap-back are all involved.
When we discussed the theory of PN junction diodes in the past, we mentioned a specific diode characteristic: it conducts in the forward direction and cuts off in reverse bias. Furthermore, as the reverse voltage continues to increase, it undergoes avalanche breakdown and conducts. This is what we call a clamping diode. This is the theoretical foundation we need for designing ESD protection. We use this reverse breakdown characteristic to keep this shunt diode in the off state during normal operation. When there’s external static electricity, this shunt diode undergoes avalanche breakdown, forming a shunt path to protect the internal circuit or gate (it’s similar to having an overflow outlet in your sink at home to prevent a water disaster when you forget to turn off the tap).
So, does this mean that the protection circuit is completely dead once it undergoes breakdown? Is it a one-time thing? Of course not. Breakdown in PN junctions comes in two forms: electrical breakdown and thermal breakdown. Electrical breakdown includes avalanche breakdown (low concentration) and Zener breakdown (high concentration), and this electrical breakdown mainly results from carrier collision ionization, creating new electron-hole pairs, so it’s recoverable. However, thermal breakdown is irreversible because heat accumulation causes the silicon (Si) to melt and burn. Therefore, we need to control the current at the moment of conduction. Typically, a high resistor is placed in series with the protection diode.
Furthermore, can you infer why ESD protection areas cannot form silicide? Also, here’s a theoretical concept: ESD typically occurs at the chip’s input pad rather than inside the chip because we always want external static electricity to dissipate as quickly as possible. Placing it inside would cause a delay (if you look at the chip I dissected earlier, you’ll see diodes near the chip’s pads). Some even have dual-stage ESD protection for double security.
03
Principles of ESD Protection
Before delving into the principles and processes of ESD, let’s first discuss ESD standards and testing methods. ESD testing methods vary based on the generation of static electricity and the damage patterns to circuits. They are typically categorized into four modes: Human-Body Model (HBM), Machine Model (MM), Charge-Device Model (CDM), and Field-Induced Model (FIM). However, the industry predominantly uses the first two modes for testing, namely HBM and MM.
① Human-Body Model (HBM)
In this mode, the static charge generated by human friction is suddenly discharged onto a chip, leading to chip burnout and breakdown. People often experience shocks when they touch something in dry conditions. HBM ESD standards have defined parameters, such as MIL-STD-883C method 3015.7, with an equivalent human capacitance of 100pF and an equivalent human resistance of 1.5Kohm. Different classifications exist based on the voltage levels, e.g., Class-1 (<2kV), Class-2 (2kV4kV), and Class-3 (4kV16kV).
② Machine Model (MM)
In this mode, static electricity generated by machine movement, such as a robot, comes into contact with a chip via its pins. The standard for MM is EIAJ-IC-121 method 20 (or EIA/JESD22-A115-A). The equivalent machine resistance is 0 (due to metal), while the capacitance remains 100pF. Because machines are metal and have zero resistance, the discharge time is very short, typically in the millisecond or microsecond range. Importantly, due to the zero equivalent resistance, even a 200V MM discharge can be more damaging than a 2kV HBM discharge. The presence of multiple wires in machines can lead to time-varying current disturbances.
04
ESD Testing Methods
ESD testing methods are similar to Good Online Instruction (GOI) testing in a fabrication facility. After specifying pins, an ESD voltage is applied for a duration, and then electrical characteristics are tested to see if any damage occurred. If there’s no issue, another step of ESD voltage is applied for a certain duration, and this process repeats until the breakdown. The voltage at which breakdown occurs is the ESD failure threshold voltage. Typically, three voltage levels (3 zaps) are applied to the circuit. To reduce testing time, the initial voltage is set at 70% of the standard voltage, and each step can be adjusted by 50V or 100V as needed.
Additionally, due to the large number of pins on each chip, testing can be done on individual pins or combinations of pins. This leads to several types of combinations:
① I/O pins (Input and Output pins): This involves testing both input and output pins separately. The charges are applied with both positive and negative polarities, resulting in four possible combinations: input with a positive charge, input with a negative charge, output with a positive charge, and output with a negative charge. When testing input, all outputs and other pins are left floating, and vice versa.
② Pin-to-pin ESD Stress: Static discharge occurs between two pins, forming a circuit. However, testing every possible pair of pins can be impractical. Since any I/O pin that receives a voltage must first pass through VDD/VSS to power the entire circuit, an improved approach is to apply a positive or negative ESD voltage to one I/O pin, while all other I/O pins are connected to the ground. Both input and output are left floating.
③ Vdd to Vss ESD Stress (from input to output): This involves connecting Vdd and Vss together, and all I/O pins are left floating. This allows the static discharge to pass through the connection between Vdd and Vss.
④ Analog-pin ESD testing: Because many analog circuits involve components like differential pairs or operational amplifiers (OP AMPs) with two input pins, it’s crucial to perform ESD testing specifically for these pairs. This means testing only those two pins, while all other pins are left floating.
Okay, the principles and testing of ESD end here. Next, let’s talk about Process and design factors.
As Moore’s Law continues to shrink, device sizes get smaller, junctions become shallower, and gate oxide gets thinner. As a result, electrostatic discharge becomes increasingly likely. In advanced processes, the introduction of silicide makes electrostatic discharge even sharper, so almost all chip designs need to overcome electrostatic discharge issues.
05
Electrostatic discharge protection can be addressed through the process at the FAB end or through the layout design at the IC design end.
So, you will see that there’s an ESD option layer in the process, or there are ESD design rules within the customer’s selection, etc. Of course, some customers may also design ESD themselves through layout based on the electrical properties of the SPICE model.
① ESD on the process side: Either you change the PN junction or you change the load resistance of the PN junction, and changing the PN junction relies on ESD_IMP. Changing the load resistance connected to the PN junction is done through methods like non-silicide or serial resistance.
▶ Source/Drain ESD implant: Due to the LDD structure on both sides of the gate poly, shallow junctions are easily formed, and the electric field at the tip of these shallow junctions is concentrated. Moreover, because these junctions are shallow, they are close to the gate, making them highly susceptible to the influence of the gate’s end electric field. Consequently, the ESD withstand capability of such LDD structures is relatively poor (<1kV). If these devices are used in I/O ports, they can be easily damaged by ESD. Based on this theory, we need a separate device without LDD but with an additional ESD implant, creating a deeper N+_S/D. This makes the tip rounder and moves it further from the surface, significantly improving ESD breakdown capability (>4kV). However, in this case, the gate of this additional MOS device must be kept long to prevent punch-through. Also, because the device is different, a separate SPICE model extraction is required.
▶ Contact ESD implant: Under the N+ drain of LDD devices, a P+ boron implant is introduced, and its depth exceeds that of the N+ drain. This design reduces the breakdown voltage of the drain (from 8V to 6V), allowing it to carry away the breakdown current from the LDD tip before it affects the drain and gate, thus protecting them. This design maintains the device size and MOS structure without alteration, so there is no need to re-extract a SPICE model. This approach is typically used in non-silicide processes, as silicide processes make it challenging to introduce the required contact implant.
▶ SAB (SAlicide Block): To reduce the interconnect capacitance of MOS devices, silicide/SAlicide processes are commonly used. However, when devices operate at output terminals, the device’s load resistance decreases, making it susceptible to ESD damage between the LDD and gate structures. In the output-level MOS, SAB (SAlicide Block) masks the RPO (Resistor Poly Overlap), preventing silicide formation. While this adds a photolithography layer and increases costs, it can raise the ESD voltage tolerance from 1kV to 4kV.
▶ Series Resistance Method: This method is cost-effective as it doesn’t require additional photomasks. It is somewhat similar to the third method (SAB with added resistors). In this approach, a resistor (e.g., Rs_NW or HiR) is intentionally added in series, achieving results similar to the SAB method.
② Design-based ESD solutions rely entirely on the designers’ expertise. Some companies provide solutions to customers within their design rules, so customers can simply follow these guidelines. However, for those without such guidelines, it’s up to the customers’ own designers. Many design rules state that they are guidelines or references, not guarantees. Typically, Gate/Source/Bulk are shorted together, and the Drain is designed to withstand ESD surges at the I/O end. This is often referred to as GGNMOS (Gate-Grounded NMOS) for NMOS and GDPMOS (Gate-to-Drain PMOS) for PMOS.
06
Regarding Snap-back ESD, there are two key pieces of information to keep in mind
① NMOS typically exhibits better Snap-back characteristics, while it’s challenging to achieve Snap-back in PMOS. Additionally, PMOS generally has better ESD resistance properties than NMOS. This is similar to the HCI effect, mainly because NMOS breakdown generates electrons with high mobility, leading to a large Isub, which easily turns on the Bulk/Source. However, this is more challenging with PMOS.
② Trigger Voltage/Hold Voltage: The Trigger Voltage is the first knee-point, the breakdown voltage of the parasitic BJT, and should be between BVCEO and BVCBO. The Hold Voltage is necessary to maintain Snap-back in the ON state without entering a gate lock (Latch-up) condition, which would lead to a secondary breakdown (thermal breakdown). Another concept is secondary breakdown current, where the current increases due to the melting of silicon after entering Latch-up. To control this, current limiting is necessary, which can be achieved by controlling W/L or adding a high-resistance current limiter. The most common method is to increase the distance between Drain or SAB (as per ESD design rules).
③ Gate-Coupled ESD Technology: As we discussed earlier, the bottleneck in multi-finger ESD designs is the uniformity of activation. In a typical scenario with ten fingers, not all fingers will activate simultaneously during an ESD event. Usually, only 2-3 fingers will activate first due to breakdown. This is because it’s challenging to make the relative positions and routing directions of each finger identical. Consequently, the ESD current concentrates on these 2-3 fingers and the ESD protection is equivalent to having the capability of only these few fingers, rather than the entire ten fingers. This is why increasing the component size does not necessarily improve ESD protection as expected.
The solution is to reduce Vt1 (Trigger Voltage). By applying extra voltage to the gate, the substrate is turned on before breakdown, enabling all fingers to activate together, and spreading the ESD current across all fingers. This allows every finger to contribute to ESD protection, making the most of a large area.
However, the drawback of this GCNMOS ESD design is that turning on the channel can lead to gate oxide breakdown, making it a less ideal ESD protection solution. Additionally, a smaller source region makes the gate voltage have a more significant impact, while a larger source region makes it harder to initiate Snap-back, making it challenging to control.
④ Another complex ESD protection circuit involves the use of a Silicon Controlled Rectifier (SCR). It is a CMOS parasitic PNPN structure that triggers Snap-Back and Latch-up. SCR can be used for layout-based protection, but not in the process, as it may lead to Latch-up failure. You can think of ways to trigger the factors discussed earlier to make it work for your circuit.
07
Words in the End
In the end, ESD design is indeed a highly complex field, and your efforts to provide some insights to FAB personnel are commendable. ESD protection solutions typically involve various methods, including resistor dividers, diodes, MOS structures, parasitic BJTs, and SCR (PNPN structure), among others. ESD considerations are not just related to design but also intertwined with the FAB process, and this field is indeed quite intricate and multifaceted. It requires expertise in both design and fabrication processes, making it a specialized area of study.
Related:
- Exploring Common Circuit Protection Components
- How Electrostatic Chucks (ESC) Work in Semiconductors?
Disclaimer: This article is created by the original author. The content of the article represents their personal opinions. Our reposting is for sharing and discussion purposes only and does not imply our endorsement or agreement. If you have any objections, please contact us through the provided channels.
