TSMC’s N3X, N2P, and A16 process nodes will be launched in 2025 and 2026.
As TSMC announced last week, the company will begin high-volume production using the N3P manufacturing process later this year, which will be its most advanced node for some time. Things will get more interesting next year because TSMC will have two process technologies that can compete with each other when they enter high-volume manufacturing (HVM) in the second half of 2025.
TSMC stated that compared to N3P, chips manufactured with N3X can reduce power consumption by 7% at the same frequency by lowering Vdd from 1.0V to 0.9V, improve performance by 5% at the same area, or increase transistor density by 10% at the same frequency. Meanwhile, the main advantage of N3X over its predecessors is its maximum voltage of 1.2V, which is crucial for ultra-high-performance applications such as desktop or data center GPUs.
TSMC’s N2 will be the first production node using gate-all-around (GAA) nanosheet transistors, significantly enhancing its performance, power, and area (PPA) characteristics. Compared to N3E, semiconductors produced with N2 can reduce power consumption by 25% – 30% (with the same number of transistors and frequency), improve performance by 10% – 15% (with the same number of transistors and power), and increase transistor density by 15% (with the same speed and power).
While N2 is undoubtedly the champion in terms of power consumption and transistor density, in performance, N3X may challenge it, especially at high voltages. For many customers, N3X will also benefit from the use of proven FinFET transistors, so N2 might not be TSMC’s best node in the second half of 2025.
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TSMC 2025: N2P and A16
Next year, TSMC will once again offer nodes targeting smartphone and high-performance computing applications: N2P (performance-enhanced 2-nanometer class) and A16 (1.6-nanometer class with backside power delivery).
Compared to the original N2, N2P is expected to reduce power consumption by 5% – 10% (at the same speed and transistor count) or improve performance by 5% – 10% (at the same power and transistor count). Meanwhile, compared to N2P, A16 reduces power consumption by 20% (at the same speed and transistor count), improves performance by 10% (at the same power and transistor count), and increases transistor density by 10%.
Keep in mind that A16 features an enhanced backside power delivery network, making it likely to be the preferred node for performance-focused chip designers. Of course, using A16 will be more expensive, as backside power delivery requires additional process steps.
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TSMC launches “Global Gigafab Manufacturing”
TSMC has also revealed details about its Global Gigafab Manufacturing plan, which is the company’s strategy to replicate its manufacturing processes across multiple Gigafab sites.
Currently, it is well-documented that large multinational fabs need a process to replicate their facilities. Chip manufacturers need to quickly transfer new and updated manufacturing processes to other factories to achieve necessary yields and avoid multi-quarter bottlenecks caused by retooling fabs.
Intel, for instance, has a well-known “Copy Exactly” program, which is one of its major competitive advantages. This program allows Intel to share manufacturing process details among its fabs worldwide, maximizing yield and minimizing performance variability. As TSMC expands its capacity globally, it urgently needs a similar program to quickly maximize yield and productivity at its new fabs in Japan and the United States.
As mentioned in last year’s seminar, “Global Gigafab Manufacturing” is a powerful global manufacturing and management platform. TSMC’s Vice President of Fab Operations, Wang Yao-long, stated, “We have implemented one-stop management of fabs to ensure consistent operational efficiency and production quality across our Gigafabs worldwide. Additionally, we pursue sustainability globally, including green manufacturing, global talent cultivation, supply chain localization, and social responsibility.”
When it comes to process technology improvements, there are two main mechanisms: Continuous Process Improvement (CPI) for yield enhancement and Statistical Process Control (SPC) for reducing performance variation. To achieve this, TSMC employs various internal technologies that rely on machine learning-based process control, continuous quality measurement, and various productivity enhancement methods. With Global Gigafab Manufacturing, TSMC can use CPI and SPC to improve yield and performance worldwide by sharing knowledge across different sites.
“Whether it’s the fab setup, process control systems, everything is copied from our Taiwan fabs,” said Kevin Zhang, Senior Vice President and Deputy Co-Chief Operating Officer of Business Development and Overseas Operations.
TSMC has not yet begun chip production at its fabs in Germany, Japan, and the United States. Therefore, how quickly yields at these fabs—Fab 23 in Kumamoto, Japan, and Fab 21 in Arizona—will reach Taiwan’s levels when they start operations in 2024 and 2025, respectively, remains to be seen. However, with the implementation of the Global Gigafab Manufacturing plan, this goal might be achieved quickly.
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