Kioxia will showcase three projects at the 2024 IEEE International Electron Devices Meeting (IEDM) held on December 7 in San Francisco, USA.
Current computing systems utilize DRAM, the primary memory for high-speed data processing by CPUs, and flash memory, which stores large amounts of data.
To process vast amounts of data at higher speeds, developments in storage-class memory (SCM) are underway, acting as an intermediary layer between DRAM and flash memory.
At this IEDM, three new storage technologies will be presented:
- DRAM technology using oxide semiconductors for reduced power consumption.
- MRAM technology suitable for increased capacity.
- Next-generation 3D flash memory technology with a new structure, achieving higher bit density and performance.
01
DRAM Technology Using Oxide Semiconductors (OCTRAM: Oxide-Semiconductor Channel Transistor DRAM)
This technology improves manufacturing processes to create vertical transistors conducive to high integration. Additionally, it achieves extremely low leakage current by leveraging the properties of transistors using oxide semiconductors. This could reduce power consumption in various applications, such as servers with large-scale main memory used in artificial intelligence and post-5G information and communication systems, as well as Internet of Things products. This development was achieved in collaboration with Nanya Technology Corporation in Taiwan.
02
High-Capacity Crosspoint MRAM Technology
This technology combines selector and magnetic tunnel junction cell technology suitable for high capacity with crosspoint array micromachining, achieving the smallest cell half-pitch reading and writing at 20.5 nanometers in MRAM history. Additionally, as cell sizes decrease, reliability issues arise; however, we propose a solution using a new reading method that leverages the transient response of selectors and reduces parasitic capacitance in the read circuit. We will continue to develop this technology for practical applications in artificial intelligence and big data processing. This development was achieved in partnership with SK Hynix from South Korea.
03
Next-Generation 3D Flash Memory Technology with Horizontal Cell Stacking Structure
Utilizing this technology, we developed a new three-dimensional structure where NAND cells are arranged and stacked horizontally, differing from traditional vertically arranged NAND cell structures. In traditional designs, increasing the number of stacking layers leads to reduced performance of NAND cells, but this structure is expected to mitigate performance degradation and enhance reliability. This approach enables the realization of cost-effective 3D flash memory with high bit density and reliability.
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