01
NBTI Background
In recent years, with the continuous development of the semiconductor industry, significant advances have been made in integrated circuit design and manufacturing processes, and more advanced technologies are being applied to integrated circuit manufacturing, promoting the miniaturization of integrated circuit sizes. As device sizes continue to shrink, especially after entering advanced technology nodes, device reliability issues have become increasingly severe, posing significant challenges to further miniaturization of devices. Among these, Negative Bias Temperature Instability (NBTI) in PMOS transistors is particularly prominent, severely limiting the lifespan of PMOS devices, and has become one of the more challenging issues in device miniaturization.
02
NBTI: Negative Bias Temperature Instability
In PMOS devices, NBTI is a phenomenon that occurs under specific conditions. When a negative voltage is applied to the gate of a PMOS device, and the device is in a certain temperature environment, the threshold voltage gradually increases over time, leading to a decline in device performance. In simple terms, it’s like applying an abnormal working condition to the PMOS “machine,” which, over time, causes it to “malfunction,” affecting the normal operation of the entire circuit and leading to degradation of the device parameters.
From the perspective of semiconductor physics, when the PMOS device is operating, a conductive channel is formed between two p+ regions (source and drain) on the n-type silicon substrate, with current carried by hole flow. NBTI, under negative gate bias, adversely affects the formation of this channel and the transport of charge carriers.
Many studies on the NBTI effect have been conducted both domestically and internationally. Various models have been proposed regarding the defect formation mechanisms and detailed processes of NBTI, which are mainly divided into two categories: (1) Interface state-related models, such as the widely accepted Reaction-Diffusion (RD) model, which suggests that Si-H bonds at the Si-SiO2 interface are broken under stress, and the generated hydrogen (H) is transported into the oxide layer. (2) Hole trapping models, including elastic tunneling of conduction and valence band carriers, which propose that holes tunnel into the oxide layer, where they are captured and released by traps, leading to device degradation and recovery. This article elaborates on the RD model and discusses methods to improve NBTI lifetime.
03
NBTI Principle
Generation of Interface States: When a negative voltage is applied to the gate of a PMOS device and it is in a certain temperature environment, a series of complex physical reactions occur at the SiO2-silicon substrate interface. According to the RD Model (Reaction-Diffusion): the negative electric field of the gate attracts electrons from the silicon substrate toward the interface, where these electrons interact with the existing chemical bonds, leading to the breaking of some Si-H bonds. Hydrogen atoms (H) break free from the bonds and become mobile hydrogen protons (H⁺). The position left by the broken bonds forms interface states. These interface states act as “roadblocks” on the otherwise smooth path of electron transport, affecting the transmission efficiency of electrons and, in turn, the performance of the PMOS device.
Charge Traps: The hydrogen protons (H⁺) that break free from the bonds will diffuse into the gate oxide layer under the influence of the electric field. During the diffusion process, they may be captured by defects or impurities in the oxide layer, forming charge traps. These charge traps carry a positive charge, which attracts electrons from the channel, changing the carrier concentration in the channel and further altering the device’s threshold voltage and current characteristics. Charge traps can be thought of as “small vortices” that “suck in” the normally flowing charge carriers, disrupting the normal current flow order.
04
NBTI Harm
As the NBTI effect persists, the threshold voltage of the PMOS device increases, meaning that a larger gate voltage is required to turn the device on. This not only increases the power consumption of the circuit but also slows down the switching speed of the device. In integrated circuits, many PMOS devices work together, and the performance degradation of one device may affect the overall operation speed and stability of the circuit. In severe cases, it may even cause incorrect logical outputs, affecting the normal function of electronic products.
05
Methods to Improve NBTI
Material Optimization:
Oxide Layer Material Improvement: Research and development of new gate oxide materials to improve resistance to NBTI. For example, using high-k dielectric materials (where k represents the dielectric constant of a material; high-k materials have a higher dielectric constant) to replace traditional silicon dioxide. High-k materials can have a thicker physical thickness at the same capacitance, reducing the probability of electron tunneling and thus decreasing the occurrence of the NBTI effect. Additionally, some high-k materials themselves have weaker hydrogen proton capture capabilities, which reduces the formation of charge traps.
Substrate Material Optimization: Special treatment of the silicon substrate or the use of new substrate materials. For instance, using strained silicon substrates to introduce stress that alters the silicon’s energy band structure, improving carrier mobility and reducing the impact of NBTI on device performance. Strained silicon substrates can cause slight changes in the arrangement of silicon atoms, allowing charge carriers to move more smoothly and reducing performance degradation caused by NBTI.
Process Improvement:
Annealing Process Optimization: In the manufacturing process, optimizing the annealing process can improve interface quality. Annealing is a thermal treatment process that can repair defects at the interface and reduce Si-H bond breakage. For example, using rapid thermal annealing (RTA), where the device is heated to a high temperature for a short time and then rapidly cooled. This can effectively reduce the formation of interface states and lower the NBTI effect without affecting the performance of other devices.
Ion Implantation Process Adjustment: Since hydrogen is one of the most common elements in wafer manufacturing and is often used to passivate Si/SiO2 interface dangling bonds, but the Si-H bond has a relatively weak bond strength and easily breaks under NBTI stress, fluorine can now replace hydrogen to form Si-F bonds, which have stronger bonding strength. This improves the resistance of the gate oxide layer to hot carrier injection and enhances its NBTI characteristics. However, an excessive amount of fluorine ions can accelerate the diffusion of boron atoms in the gate oxide layer and increase the leakage current of PN junctions, so the ion implantation concentration must be carefully controlled.
Circuit Design Optimization:
Redundant Design: In circuit design, redundant design methods are used by adding backup PMOS devices. When some devices experience performance degradation due to the NBTI effect, backup devices can be activated in time to ensure the normal operation of the circuit. This is similar to preparing some “spare tires” for the circuit, which can step in when needed to maintain system stability.
Dynamic Voltage Adjustment: Dynamically adjusting the operating voltage of PMOS devices based on the actual workload of the circuit. Under light load conditions, the voltage can be reduced appropriately to reduce the occurrence of NBTI effects; when a heavy load requires high performance, the voltage can be increased. This approach can reduce the long-term impact of NBTI on devices and extend their lifespan while ensuring the functionality of the circuit.
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