In the semiconductor photolithography process, many stages critically impact the precision and quality of chip manufacturing. Among them, the key step of Leveling plays an indispensable role in ensuring the flatness of the wafer surface.
As semiconductor manufacturing technology continues to evolve, wafer sizes are increasing while thickness is decreasing. During processing, various factors can cause significant wafer warpage. For instance, large thermal processes (high temperature, long duration), trench etching and dielectric filling on the silicon substrate (due to material and pattern differences), stress mismatches in deposited film layers, and residual stress during wafer thinning can all result in wafer warpage.
Wafer warpage leads to a series of serious problems. In the photolithography stage, it significantly affects focusing at the wafer edge, greatly increasing the difficulty of alignment for subsequent lithography equipment, thereby impacting overlay accuracy and ultimately altering device performance, such as causing defocus issues. Even wafers with warpage within the processing tolerance of the equipment may have internal defects due to differences in thermal expansion coefficients or stress mismatches. Under external force, these can easily cause breakage during processing, leading not only to contamination of equipment and handling tools but also resulting in equipment downtime and requiring a complex and expensive cleaning and recovery process. Therefore, controlling wafer warpage and ensuring surface flatness is essential.
Leveling is a crucial method to address this challenge. Currently, the primary strategy for controlling wafer surface flatness is to optimize the uniformity of photoresist thickness and perform Leveling scans before exposure. The principle involves using specialized equipment and technology to perform comprehensive scans of the wafer surface to confirm its topography. During scanning, the height information of various positions on the wafer surface can be accurately obtained to construct a 3D topographic map of the surface. Instruments such as interferometers (Fizeau interferometry), white light interferometers, step profilers/probe profilometers, atomic force microscopes, and scanning electron microscopes can all be used to gather surface and step height data, which provide critical support for Leveling.
Based on the topography data obtained from Leveling scans, compensation can be applied to the exposure system. By adjusting relevant parameters of the exposure tool, such as the angle and intensity distribution of the light source, the exposure process can adapt to the actual condition of each shot on the wafer surface. As a result, even with a certain degree of wafer warpage, its impact on lithography accuracy can be reduced to some extent, allowing the photomask pattern to be transferred more accurately onto the photoresist layer.
However, the current approach of combining Leveling with optimized photoresist thickness uniformity still has limitations. Although it can improve surface flatness to a certain extent, it cannot fully and effectively control it, making it difficult to compensate for overlay residuals caused by surface unevenness. This remains one of the pressing issues in semiconductor photolithography.
To achieve more precise Leveling, there are strict definitions and various measurement methods for warpage-related parameters. Warpage is a key topographic parameter of the wafer, and related factors include wafer thickness, TTV (Total Thickness Variation), BOW (bending), WARP (warpage), TIR (Total Indicated Reading), STIR (Site Total Indicated Reading), and LTV (Local Thickness Variation). Taking TTV as an example, it is defined as the difference between the maximum and minimum thickness values encountered during a scan pattern or a series of point measurements. It can be calculated using non-contact measurement probes that monitor the gap between upper and lower probes and the wafer surface, combined with a calibration process. BOW refers to the deviation of the center point of the median surface of a free, unclamped wafer from a reference plane defined by three equidistant points on the circumference. WARP is the difference between the maximum and minimum distances from the median surface of a free, unclamped wafer to the reference plane. Measurement methods for these parameters include laser interferometry for surface profiling, contact-type step profilers, fringe projection structured light imaging, capacitive displacement sensors, laser triangulation displacement sensors, and confocal spectral displacement sensors, each with its own advantages and disadvantages in terms of cost, efficiency, and accuracy.
As a key step in ensuring wafer surface flatness during the lithography process, Leveling is already widely used but still requires continuous improvement and refinement to meet the increasing precision and quality demands of semiconductor manufacturing and to drive ongoing advancement of the entire semiconductor industry.
Related:
- Understanding the Role of Film Agents in Chip Cleaners
- Guide to Clearing Water Marks on Cleaned Wafers
- Wafer Plating Issues Caused by Hydrogen Reaction
- Best Laboratory Silicon Wafer Cleaning Methods Guide
- Why Film Agents Are Added to Chip Cleaning Agents
- Dummy vs Test vs Production Wafers and Their Roles
- How to Safely Store and Transport Semiconductor Wafers
- Wafer Scale Chips: Powering Trillion-Parameter Models
- Challenges Faced When Increasing Wafer Plating Speed
Disclaimer: This article is created by the original author. The content of the article represents their personal opinions. Our reposting is only for sharing and discussion purposes and does not imply our endorsement or agreement. If you have any objections, please get in touch with us through the provided channels.
