01
Basics of Chip Manufacturing and Materials
Wafer: Slices of single-crystal silicon, commonly 8-inch/12-inch in size. Crystal orientation (e.g., <100>, <111>) affects device performance.
Substrate Materials: Besides silicon, include compound semiconductors (GaAs, SiC, GaN), Silicon-on-Insulator (SOI), etc.
Photoresist: Positive/negative types, sensitive to light; undergoes chemical change after exposure to define patterns.
Mask/Reticle: Quartz glass coated with chrome, etched with circuit patterns; includes binary and phase-shift masks.
Target: High-purity metals (e.g., Al, Cu, W) for PVD deposition; purity >99.999%.
Electronic Specialty Gases: For etching and deposition, e.g., CF₄ (etching), SiH₄ (deposition), N₂O (oxidation).
Chemical Reagents: For wet cleaning (e.g., HF, H₂SO₄), developer (TMAH), etchant (KOH), etc.
CMP Slurry: Contains abrasives (SiO₂, Al₂O₃) and chemicals to planarize wafer surfaces.
Epitaxy: Growing single-crystal films on wafer surfaces to improve electrical performance (e.g., heterojunctions, doping control).
Bonding Materials: Solders (SnAgCu), conductive adhesives, gold/copper bonding wires for packaging.
02
Design and Manufacturing Interface
EDA Tools: For circuit design (Cadence/Synopsys), layout planning, process simulation (TCAD).
Design Rules: Geometric constraints like minimum linewidth/spacing; scale with nodes (e.g., 3nm node <5nm linewidth).
Design for Manufacturability (DFM): Optimizing layout to match process capabilities and reduce defects (e.g., OPC, RET).
Layer Stack: Divides chip layout into transistor, metal interconnect, insulation layers by function.
Device Models (SPICE): Describe transistor electrical properties for circuit simulation and process alignment.
03
Front-End Process (FEOL) – Transistor Manufacturing
1. Lithography
Principle: Transfers patterns onto photoresist via mask projection; resolution limited by λ/2NA.
Types of Lithography Tools: DUV (193nm), EUV (13.5nm), i-line (365nm).
Resolution: Minimum resolvable linewidth; EUV theoretical <5nm, limited by diffraction.
Overlay Accuracy: Alignment error of multilayer patterns; <2nm required for 3nm node.
Photoresist Development: Positive resist dissolves after exposure; negative remains, forming a pattern template.
2. Etching
Dry Etch (Plasma): Combines physical ion bombardment + chemical reaction; isotropic/anisotropic.
Wet Etch: Uses chemicals; high selectivity but lower precision; used for cleaning or non-critical layers.
Reactive Ion Etching (RIE): Ions in plasma accelerate vertically to etch materials.
Deep Reactive Ion Etching (DRIE): For MEMS or 3D structures, such as TSV etching.
Etch Selectivity: Ratio of etch rate for target vs. mask/substrate; typically >10:1.
3. Thin Film Deposition
CVD: Gas-phase reactions on wafer surface form films, e.g., SiO₂ (PECVD), Si₃N₄.
PVD: Sputtering/evaporation to deposit metals (e.g., Al-Cu alloy, TiN barrier).
ALD: Atomic layer growth for Å-level thickness control, e.g., high-k dielectrics (HfO₂).
Oxidation: Thermal oxidation in dry/wet O₂ forms SiO₂ for gate insulators/isolation layers.
MOCVD: For compound semiconductor epitaxy (e.g., GaN HEMT devices).
4. Doping
Ion Implantation: High-energy ions form p-type (B) / n-type (P, As) regions.
Annealing: High temp repairs damage and activates dopants (e.g., laser, RTA).
Diffusion: At high temp, dopants diffuse in silicon to form graded profiles (e.g., source/drain).
Ultra-Shallow Junctions: <10nm junction depth in advanced nodes, to suppress SCE.
Selective Doping: Masked regions doped for better performance (e.g., LDD structures).
5. Planarization
CMP: Mechanical abrasion + chemical erosion to globally planarize wafer surfaces.
CMP Applications: Metal layer planarization, STI surface treatment, TSV bottom flattening.
Etch Back: Removes excess films via dry etch to assist local planarization.
6. Cleaning
RCA Clean: Standard wet cleaning, SC-1 (organic removal), SC-2 (metal ion removal).
Megasonic Cleaning: MHz-level cavitation removes submicron particles.
Plasma Cleaning: Dry removal of resist residue (ashing) or surface activation.
04
Back-End Process (BEOL) – Interconnect and Multi-Layer Integration
Metal Layers: Multi-layer Cu/Al connects transistors, isolated by low-k dielectrics (e.g., SiOCH).
Cu Interconnect (Damascene): Trenches etched first, then filled with Cu, avoiding Al electromigration.
Barrier Layer: Ti/TiN prevent Cu diffusion and enhance adhesion.
Low-k Dielectrics: k<3 to reduce capacitance, e.g., porous SiO₂, SiOC.
ULK Dielectrics: k<2.5, challenges in mechanical strength and reliability.
Via: Vertical connections between metal layers; <50nm in advanced nodes.
W Plug: Tungsten filled via for shallow interconnects.
Dual Damascene: Forms metal lines and vias simultaneously for efficiency.
Stress Engineering: Depositing stress layers (e.g., SiN) to enhance carrier mobility.
05
Advanced Nodes and 3D Integration
FinFET: 3D structure suppressing SCE; mainstream below 7nm.
GAAFET: Nanosheet structure with gate-all-around for improved control (e.g., 3nm GAA).
FD-SOI: Thin Si + buried oxide to reduce leakage; suitable for low-power chips.
3D IC: Chips vertically stacked via TSV to shorten interconnects.
Hybrid Bonding: Cu-Cu direct bonding for ultra-high density (>10⁴/mm²).
Heterogeneous Integration: Combines devices of different materials (e.g., silicon photonics, RF) on same chip.
Fan-Out Packaging: Dies embedded in mold with redistributed routing (e.g., InFO, eWLB).
System-in-Package (SiP): Multi-chip integration on a substrate (e.g., CPU+GPU+memory).
06
Packaging and Testing
Flip Chip: Die face-down with solder balls directly connecting to substrate, reducing delay.
Wire Bonding: Gold/copper wires connect die pads to substrate; low cost, suitable for low density.
Substrate: Packaging carrier – organic (BT), ceramic (Al₂O₃), silicon-based.
Underfill: Epoxy filler after flip chip to enhance reliability, resist thermal stress.
Molding: Epoxy encapsulation to protect die from environment.
Testing Types:
Wafer Test (CP): Probe test for bare die functionality.
Final Test (FT): Electrical test for finished chips.
Reliability Test: HTOL, TC, HAST for long-term stability.
Failure Analysis (FA): Uses SEM, FIB, EMMI to locate failure points and optimize process.
07
Equipment and Key Technologies
Lithography Tool Components: Light source (EUV laser plasma), objective system (multi-layer mirrors), stage (nano-positioning).
Etcher Types: RIE, ICP, MIE.
CVD Equipment: Tube furnaces (batch), single-wafer chambers (high precision), e.g., LPCVD, PECVD.
Ion Implanter: Low energy/high beam current (source/drain) vs. high energy (buried layer); magnetic analyzer filters ions.
Metrology Tools:
CD-SEM: Measures linewidth.
Ellipsometer: Measures film thickness/refractive index.
XRD: Analyzes crystal structure and stress.
Defect Inspection: AOI/EBI detect nano-particles and pattern defects.
Process Simulation: TCAD models etching, deposition, doping to optimize parameters.
08
Manufacturing Management and Yield
Cleanroom: Class 100 (≤100 particles/ft³ ≥0.5μm); micro-contamination control.
Yield: Yield = (good dies/total dies)×100%; affected by defect density, process variation.
Poisson Yield Model: Y = e^(-DA); D = defect density, A = chip area.
Process Window: Parameter tolerance range (e.g., ±10% exposure dose for litho).
SPC: Statistical monitoring to prevent drift.
FMEA: Identify weak steps, preemptively prevent failure.
Thermal Management: Local temp up to 150°C during operation; controlled via packaging (e.g., heatsink, TIM).
09
Physical Effects and Process Challenges
Short Channel Effect: For L<100nm, source-drain field penetrates channel, causing Vth shift.
Quantum Tunneling: Gate oxide <1nm at 3nm node causes leakage surge.
Electromigration: High current causes metal atom migration, interconnect opens (Cu needs barrier).
Stress Migration: Stress mismatch during thermal cycling causes failure.
Hot Carrier Effect: High field energizes carriers, damaging lattice and reducing lifespan.
Latch-Up: Parasitic PNPN turns on, permanently damaging chip; needs protection design.
10
Special Processes and Emerging Tech
MEMS: Micro structures (e.g., cantilevers, films) released via etching for sensors/actuators.
Silicon Photonics: Integrate waveguides, modulators on silicon for optical interconnect.
Power Devices: Trench IGBT, SiC MOSFETs with high-temp annealing (>1600°C).
In-Memory Computing: Reduces data movement by computing in memory (e.g., RRAM, MRAM).
Nanoimprint Lithography (NIL): Mold-based patterning; cheaper than EUV, for large-area nanostructures.
ALE: Layer-by-layer etching for 3D sidewall tuning (e.g., GAA nanosheets).
Laser Annealing: Nanosecond pulse heating melts surface only; activates ultra-shallow junctions.
Hydrogen Passivation: H atoms neutralize Si dangling bonds, improving interface.
Low-Temp Process: <300°C deposition for flexible substrates or hetero-integration (e.g., oxide semiconductors).
11
Quality Control and Standards
SEMI Standards: Rules for materials, tools, process (e.g., SEMI S2, SEMI M11).
ISO 9001: Quality system certification to ensure traceability and standardization.
ESD Protection: Anti-static gear and grounded benches prevent electrostatic discharge damage.
Contamination Control: Resist volatiles, lubricant leaks can cause particles – tightly managed.
Lot Traceability: Every wafer’s parameters, equipment, personnel logged for yield analysis and troubleshooting.
These knowledge points cover the full chain of chip manufacturing – from material principles to process technology, from equipment fundamentals to advanced challenges – with a focus on technical essence and engineering practice.
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