Role
“Foundry”, in the field of integrated circuits, is a specialized manufacturer of chips
“Fabless” is a combination of Fabrication and less. It refers to an operation mode of integrated circuit design that focuses on design without manufacturing operations. It is also used to refer to IC design companies that do not own chip manufacturing plants. The term IC Design house is often referred to as Fabless.
Wafer
“Wafer”, a complete Wafer, is made of pure silicon (Si). Generally divided into 6-inch, 8-inch, and 12-inch specifications
“DIE”, a small piece of Wafer, is a Wafer, or die, that is packaged into a chip, “chip.”
The wafer is first cut, then tested, and the qualified die is removed
Wafer Level
Original chips: Wafers produced by manufacturers such as Samsung and Hyundai are graded according to capacity. Wafers with more than 93% capacity are called Class A, or A-chips for short. They are packaged and guaranteed by the original manufacturer.
Downgrade Flash chips: wafers with less than 93% capacity will be called downgrade Flash. They will no longer be reinfected with the reinfected label of the original manufacturer, which will be processed by some small packaging factories. Among them, the relatively sufficient and stable use is generally called white tablets. The price is usually 70 to 80 percent of grade A.
Black chips: the chip whose capacity is seriously insufficient and quality cannot be guaranteed is the black chip. Another part of the bad business of recycling waste flash chips is polished flash chips generally also known as black.
Process and stage
CP (Chip Probing): As the name implies, tests the electrical parameters of the chips. Each die on a wafer is tested to eliminate defects and reduce the cost of subsequent packaging
WAT (Wafer Acceptance Test): the Test of the special Test graph (Test key), through electrical parameters to monitor the normal and stable process of each step
FT (Final Test): tests the encapsulated chips. There are usually far fewer tests than CP because they have been tested before
Tape Out: The chip was designed and the design data was handed over to FAB to start production.
Wafer out: Wafer has finished production in FAB, the integrated circuit design has been manufactured on a silicon base, and the packaging test has begun
Mask: used to fabricate master plates of various levels of integrated circuits, such as N-well, active region, polysilicon, metal 1, through-hole, and metal 2…. Metal 10… These craft layers. The chip is the product of the precision superposition of the above layers.
Full Mask: meaning that all masks in the manufacturing process serve a design
Multi-project wafer (MPW) is a Wafer processing service that puts multiple integrated circuit designs with the same process on the same Wafer. Each design variety can get dozens of chip samples for experiments and verification tests in the product development stage.
The process & cost of Taping out
Foundry quotes are based on process and cast volume, single mask price.
Cost =Mask plate making fee +N* single wafer cost. So there are two kinds of costs,
1 is the cost of MASK, about $300,000 – $500,000.
2 is the cost of Wafer, which is the cost of Wafer, which is around $1500-2000 per Wafer.
Etching costs are lower than lithography at 28nm, whereas at present 14 and 7nm are mostly ionic etching
Then there are the costs of testing and packaging
Three major EDA manufacturers
Synopsys、Cadence、Mentor
Mainstream IP providers
ARM、eMemory、Synopsys、Cadence
The chip types
ASIC: special integrated circuit refers to an integrated circuit designed and manufactured to meet the requirements of specific users and the needs of specific electronic systems.
MCU: Microcontroller Unit, also known as the Single-Chip Microcomputer (Single-Chip Microcomputer), is the Central Process Unit; CPU) frequency and specifications do appropriate reduction, and the memory (memory), counter (Timer), USB, A/D conversion, UART, PLC, DMA, and other peripheral interfaces, and even LCD drive circuit are integrated on A single-chip, forming A chip level computer, for different application occasions to do different combination control.
DSP chip: also known as a digital signal processor, is especially suitable for digital signal processing operations of the microprocessor, its main application is a real-time and fast implementation of various digital signal processing algorithms.
The System on Chip (SoC) is the brain of intelligent devices. It is a Chip circuit that integrates the key components of a System on a Chip to achieve complete System functions. Digital IC design method based on sequential driving has been developed to design method based on IP core reuse and has been widely used in SOC design. In the design of SoC (System on Chip) based on IP core reuse, the design of the on-chip bus is the most critical problem.
RISC stands for Reduced Instruction Set Computer.
CISC stands for “Complex Instruction Operation Set.
OLT: Service life test.
NTO: New Tape out
END.
