In the field of chip design, ECO (Engineering Change Order) is a key concept. The following provides a detailed introduction from the aspects of definition, function, implementation process, and practical application:
I. Definition of ECO
ECO refers to a localized circuit modification scheme made after a chip has completed tape-out, in response to minor design defects or functional requirement changes discovered in the manufactured chip. It allows correction or optimization of chip functions without a complete redesign and re-tape-out, by modifying metal layer interconnections, configuring programmable logic units (such as FPGAs), or adjusting memory units (such as ROMs or registers).
II. Core Functions of ECO
Fixing design defects
If logic errors, timing violations (such as setup/hold time violations), or missing functions are found after tape-out, ECO can be used to modify the circuit and avoid the high cost of re-tape-out (which may cost millions to tens of millions of dollars).
Example: If a data consistency issue is found in the cache controller of a processor during testing, ECO can be used to add an extra control signal path for correction.
Accommodating requirement changes
When customer requirements are adjusted (e.g., adding a new interface protocol or optimizing power modes), ECO allows rapid function iteration without a complete chip redesign.
Example: A 5G chip may need to support a new frequency band protocol before mass production. This can be achieved via ECO by modifying the configuration logic of the RF front-end registers.
Reducing cost and time
Re-tape-out requires months and incurs extremely high costs. ECO can shorten the modification cycle to a few weeks and save over 90% of the expense, making it especially suitable for urgent fixes before mass production.
Supporting chip version iterations
When different models (such as high-power or low-power versions) are derived from the same chip platform, ECO can adjust certain circuits (e.g., shut down unused modules) to avoid redundant design efforts.
III. Implementation Methods and Techniques of ECO
Depending on the chip type (ASIC or FPGA) and process characteristics, ECO is mainly implemented through the following methods:
- Hardware-level modifications
- Metal layer routing adjustments
In ASICs, signal paths can be changed by adding or modifying metal layer routing (requires multi-layer metal process support).
Example: Disconnecting an incorrect clock signal and reconnecting it to the correct clock buffer. - Fuse or antifuse programming
Permanent modifications to circuit connections are achieved using fuse (physical disconnection) or antifuse (dielectric breakdown) structures, commonly used in one-time programmable (OTP) chips. - Programmable logic unit configuration
In FPGAs, logical unit (LE/LUT) connections or register states can be modified by rewriting the configuration file (.bit file).
- Software-level configuration
- Register / ROM parameter adjustments
Function logic is corrected by changing default values of internal registers or microcode stored in ROM.
Example: Updating the enumeration protocol parameters of a USB controller. - Clock / power domain control
Adjusting clock division ratios or power domain switching strategies optimizes power consumption or timing (e.g., reducing the operating frequency of non-critical modules).
IV. ECO Implementation Process
- Problem identification and evaluation
Use chip tests (e.g., ATE tests, FPGA prototype verification) to locate defects and assess the feasibility of ECO modifications (e.g., whether low-level circuits are involved, whether metal layer routing resources are sufficient). - Design modification plan
Use EDA tools (e.g., Synopsys IC Compiler, Cadence Virtuoso) to generate ECO scripts, defining the netlist nodes or routing paths to be modified. - Simulation and verification
Perform timing simulation, functional simulation, and DRC (Design Rule Check) to ensure the modification introduces no new issues. - Physical implementation and verification
Mark the modified metal layer positions on the chip layout, generate GDSII files, and use photomasks to produce localized modifications for post-processing. - Pre-mass production testing
Conduct full testing on chip samples modified by ECO. Only after confirming the defect is fixed and the function is normal, can it proceed to mass production.
After such a series of processes and considerations, the ECO can finally be completed, ensuring a smooth tape-out and delivering a good chip.
V. Limitations of ECO
- Limited modification scope: Only applicable to small-scale modifications (e.g., a few gates or a single signal path), and not suitable for large-scale architectural changes (e.g., adding a processor core).
- Increased testing complexity: ECO versions must be tested in parallel with the original version to ensure consistency and compatibility of the modifications.
VI. Conclusion
ECO is a key technology in the chip design process for reducing cost and shortening the iteration cycle. Its core value lies in rapidly responding to design defects and requirement changes through localized hardware or software modifications. Especially at advanced process nodes, it plays a significant role in improving chip development efficiency and market competitiveness.
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