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FanFET 3D NAND is coming soon!

This article will present the technology, standards, and highlights of FanFETs (Innovative Fan Field Effect Transistors) for 3D-NAND flash memory applications and introduce a simple concept for extending them to digital logic circuits.
3D Nand flash cell standard DiskMFR

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Imagining a future society filled with high-speed massive information and computation flows, where mobile devices (including NOR+OLED displays) are searching and exploring powerful logical operations and intelligent analytics (NAND, CPU/AI) in the cloud (dynamic random memory, DRAM) in real-time wherever you are, quickly accessing new information and then making decisions. High-speed, high-capacity memory and CPU/AI chips are used in the smart home, automated driving, mobile execution, and big data analytics, both of which play an important role in the era of wireless communication and smart computing.

This article will present the technology, standards, and highlights of FanFETs (Innovative Fan Field Effect Transistors) for 3D-NAND flash memory applications and introduce a simple concept for extending them to digital logic circuits.

Transistor Development Roadmap

Figure 1 is a technology roadmap that shows the current state of development of mainstream transistors and product applications. From the CMOS (Complementary Metal Oxide Semiconductor) technology perspective, there is NOR flash technology in addition to general purpose logic and power device products. For DRAM (dynamic random access memory), NAND (computer flash memory devices) and logic products below 25nm, their transistors have evolved into Surround Gate Transistors (SGTs), Surround Gates (GAA, GAAFETs) and FinFETs, respectively.

For example, sub-1xnm NAND flash (technically 3D-NAND flash) consists of series-connected vertical-current GAA (Unified Authentication Architecture) memories; FinFET logic circuits have gradually evolved from CMOS to two-dimensional enhanced structures that are connected in parallel with multi-fins or nanosheets (e.g., MBCFETs) to increase the current. These techniques require deep ultraviolet (DUV) or extreme ultraviolet (EUV) lithography equipment to produce the corresponding nanopatterns.

Nonetheless, the new FanFET is a fan-like active component. It has a vertical current and a corresponding end region that meets the criteria for the fabrication of three-dimensional memory stacks and high-density memories. As a result, it can be used in transistors and memories.

Figure 1: Transistor Node Technology Roadmap

New 3D-NAND flash memory can create new transistors

GAA cells are currently the dominant and only 3D-NAND Flash technology owned by the world’s leading memory manufacturers. 3D storage stack, which is the reason for the rapid growth in demand for 3D flash density.

The improvement in memory node technology and the increase in density depend on two key technologies: emerging materials and innovative architectures. Currently, only a few manufacturers manufacture and use memories derived from emerging materials such as FRAM (ferroelectric memory), MRAM (magnetic random memory), PRAM (phase change memory) and RRAM (resistive variable memory).

For the innovative architecture, in addition to increasing memory density, a simplified approach and highly compatible processes also meet the requirements for future applications and the popularity of memory. Starting from the concept of the closest filled cell, the Hexas technology takes into account the layout and connection of the circuits and requires a rationalization of the 3D device model and 3D process integration. When the 3D NAND flash work is completed, an entirely new transistor is formed, the transistor FanFET, an innovative transistor that is completely different from FinFETs and GAAs. Figure 2 shows the structure, coordinates, and terminals of the FanFET.

Figure 2: FanFET structure, coordinates and termination

FanFET: both transistor and memory

The main differences between MOST and FanFETs are the location of the terminals, the 3D partial differential equation of the drift-diffusion current, the direction of the current, and the 3D modular manufacturing process. The FanFET memory cell exists in an HCP with a feature size of approximately 2F2, which means that the FanFET memory cell has twice the density per unit area of a GAA memory cell.

3D-NAND flash modulation manufacturing flow

The key to modular process integration for 3D-NAND flash memory is the construction and relative arrangement of memory cells. Figure 3 shows the graphical structure criteria for GAA and FanFET on 3D-NAND flash memory. First, the front-end on-line process (FEOL) starts with a thin-film stack of polysilicon and silicon nitride, followed by the memory cell fabrication process, the mid-cycle process (MEOL), and the back-end on-line process (BEOL).

Figure 3: 3D NAND flash cell standard

In thin-film stacking in the FEOL process, the combination of thicknesses, the uniformity of the deposited films, and the number of stacked layers must be considered. In the next unit process, the following issues need to be considered: methods and procedures for the integration of unit construction, channel zones, and physical mechanisms for transistor operation, and etching of aspect ratios. The last one is the bit line (BL), the word line (WL) and metal interconnects in the MEOL process and the BEOL process. This can give rise to critical issues such as conductivity of doped polysilicon or BL and WL metal lines, high aspect ratios, CD deviations in lithographic alignment, and contamination of metals or particles.

Key processes and differences in memory cell modules

Split GAA is derived from GAA (Split GAA is the author’s tentative name). Figure 4 compares the three Split GAA and FanFET process modularizations. Comparing the main differences between the four storage units in a comprehensive view (the GAA process is omitted here), the first three companies mentioned above use the Split GAA unit manufacturing model based on the GAA process. The GAA unit transforms into an elliptical shape, which technically creates a Split GAA unit when it is split.

The common standard manufacturing process includes film stacking, defining the active area (AA), forming an array of cells, completing an isolation layer, connecting lines, and re-stacking.

An example is the FanFET process flow at Hansa Technology Corporation. These steps include intracellular isolation, hidden cell process integration, and cell-to-cell isolation. This is a post-gate level processing technology.

Storage unit evaluation between Split GAA and FanFET

The similarities between the four companies above are as follows: all use vertical currents, all have multi-layer stacked processing technology, connect single wires, and have the same bit and word lines. Although similar in appearance, the operating area of the current Hexas memory is significantly different from that of the first three companies.

In order to process the memory cell module, the first three cells must be fixed to a certain value to satisfy the requirements for further processing. The cell diameter is one of the short axes of the Split GAA cell hole, which can affect the final density of the cell. However, there is no such problem with the FanFET memory cell module in process integration because the cell shape and feature size of the FanFET memory cell can be freely adjusted to the developer’s needs, and the density can in fact be varied. Because the cell itself is in a closed-loop configuration, the isolation layers between and within cells must be fully compliant with the design specifications, so the feature sizes of the three companies mentioned above are in the range of approximately 3.5 F2 to 6 F2.

In addition, due to the sequence and differences in various steps, such as first- and second-gate process technologies, the cascading of isolation layers and cells, as well as film residues and CD bias on the process flow may lead to varying degrees of edge effects.

Limitations of Split GAA

Split GAA can have serious problems in that it is a closed-loop structure in the crystalline cell and that this structure can limit the size of the cell. When the cell shrinks, the filler dielectric films and BLs can be problematic. At the same time, the storage density per unit area decreases as the feature size of the Split GAA cell increases. Conversely, FanFETs are free to adjust the shape and ratio between the cell and the isolation layer. A key factor is that the FanFET is an open recessed cell, independent of the exposure and development of lithography technology and the filling process of the dielectric film. It can be accomplished in existing 12-inch ArF fabs and DUV lithography equipment with node technology within 90 nm (included) to 10 nm (not included) of the process.

Highlights and benefits of FanFET technology

Hanseatic’s FanFETs have 10 technical highlights. From a technical point of view, the first set of advantages is an innovative high-density transistor cell, which includes the following five points

  1. Featuring a new FanFET (Electric Field Effect Transistor) structure.
  2. Suitable for both transistor and memory use
  3. 3D structures and techniques capable of producing multi-layer stacks
  4. Can increase storage density per unit area
  5. Diversified technology: In addition to stand-alone memory technology, it can be extended to embedded systems and in-memory computing.

Scalable Moore’s Law indicates a range of FanFETs between 90 nm (inclusive) and 10 nm (exclusive) in the node technology. From a commercial point of view, the second set of advantages includes the following five points.

  1. A win-win business model and strategic profitability can be obtained
  2. Enables process compatibility with silicon: the process technology is compatible with current 12-inch wafer fabs
  3. Reduced development costs and increased capacity utilization
  4. Ability to share patent rights: share patent pools and establish related technical specifications
  5. Ability to create a complete manufacturing supply chain

Increasing future business opportunities

Hanseatic’s innovative FanFET 3D-NAND flash memory is compatible with the standard MOST architecture and is the most efficient development technology. The flash memory has a simple but precise cell with a characteristic size of 2 F2, which provides the highest density per volume in the 3D process. In the era of mobile communications and artificial intelligence, Hexas Technology is looking to develop a win-win business model with similar companies to improve technology, capture business opportunities, and further integrate new material technologies used to develop nanoscale storage applications for the maritime industry.

Souring from https://www.eetimes.com/the-concept-of-a-new-transistor-fanfet-technology-applied-to-3d-nand-flash/#

DiskMFR Field Sales Manager - Leo

It’s Leo Zhi. He was born on August 1987. Major in Electronic Engineering & Business English, He is an Enthusiastic professional, a responsible person, and computer hardware & software literate. Proficient in NAND flash products for more than 10 years, critical thinking skills, outstanding leadership, excellent Teamwork, and interpersonal skills.  Understanding customer technical queries and issues, providing initial analysis and solutions. If you have any queries, Please feel free to let me know, Thanks

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5 Responses

  1. I am truly pleased to glance at this webpage posts which carries plenty of valuable information, thanks for providing these information. Brigit Bevan Wesa

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