Full Chip Manufacturing Process: From Beginner to Expert

In the previous issue, I introduced the wafer preparation process.

Today, we continue with the next step and discuss the chip (die) manufacturing process.

This stage is the most challenging part of the chip manufacturing process. I will try to explain it in simple terms and hope everyone will be patient enough to read through.

01

█ Oxidation

First, on the polished and cut wafer, we need to perform an oxidation process.

The purpose of oxidation is to form a protective film (oxide layer) on the fragile wafer surface. The oxide layer helps prevent the wafer from being affected by chemical impurities, leakage currents, and etching.

The oxidation process includes thermal oxidation, plasma-enhanced chemical vapor deposition (PECVD), electrochemical anodic oxidation, etc.

The most commonly used method is thermal oxidation, which forms a thin and uniform silicon dioxide layer at temperatures between 800°C and 1200°C.

Depending on the gases used during oxidation, it can be categorized into dry oxidation and wet oxidation.

Dry oxidation is achieved by inputting pure oxygen, which flows over the wafer surface and reacts with silicon to form a silicon dioxide layer. Wet oxidation uses both oxygen and high-solubility water vapor.

Dry oxidation is slow but produces a thin and dense oxide layer, while wet oxidation is faster, but the protective layer is thicker and less dense.

Currently, dry oxidation is the mainstream technology in semiconductor manufacturing, while wet oxidation is more commonly used for non-critical layers or specific thick film requirements.

02

█ Photolithography (Coating, Pre-bake, Exposure, Post-bake, Development)

Next, we reach the most crucial step – photolithography.

The photolithography machine, which has been the center of attention in recent years, is related to this process.

In simple terms, photolithography is like printing the circuit diagram onto the wafer, much like how a printing machine works.

Photolithography consists of three main steps: coating, exposure, and development. Let’s break them down.

First, coating.

The material used for coating is called photoresist, also known as photoresist material, which is light-sensitive.

There are two types of photoresist: positive and negative.

When exposed to a specific light beam, positive photoresist undergoes a molecular change that makes it easier to dissolve, while negative photoresist becomes more resistant to dissolution. In most cases, positive photoresist is used.

When coating, the wafer is first rotated at a speed of 1000~5000 RPM. A small amount of photoresist is applied to the center of the wafer. The centrifugal force causes the photoresist to spread evenly across the wafer’s surface, forming a uniform layer that is 1 to 200 microns thick.

It’s worth noting that photoresist is a highly specialized material. Most of the photoresists used in China come from Japan.

After coating, the wafer undergoes a soft bake to slightly cure the photoresist. This step is called “pre-bake.”

Next, the photolithography machine is used for exposure.

The wafer and the mask are placed in the photolithography machine.

The mask, also called the photomask, is a core element of photolithography and an important output of the chip design phase (which will be introduced later).

The mask is a glass or quartz plate with an opaque material (such as chromium) patterned on it. The pattern represents the blueprint of the chip, i.e., the integrated circuit layout.

In the photolithography machine, both the wafer and the mask are precisely fixed. The special light source of the machine (mercury vapor lamp or excimer laser) emits a beam of ultraviolet light, which passes through the transparent parts of the mask and multiple lenses (to focus the light), and is then projected onto a small area of the wafer.

The fine circuit pattern is “projected” onto the wafer.

For positive photoresist, the exposed areas become easier to dissolve, while the unexposed areas remain unaffected.

The mechanical positioning system keeps moving the wafer and mask, and the light beam continuously shines on them. Ultimately, dozens or even hundreds of chip circuits are “drawn” across the entire wafer.

After the wafer exits the photolithography machine, it undergoes another baking process (at 120~180°C for 20 minutes), known as post-bake.

The purpose of post-bake is to ensure that the photoresist undergoes a complete photochemical reaction and compensate for insufficient exposure intensity. It also reduces wave-like patterns caused by standing wave effects after development.

Next comes the development step.

After exposure, the wafer is immersed in a developer solution, which removes the exposed photoresist (for positive resist) and reveals the pattern.

The wafer is then rinsed and dried, leaving behind an accurate circuit pattern.

03

█ About the Photolithography Machine

Let’s take a moment to discuss the photolithography machine.

Traditional photolithography technology typically uses deep ultraviolet (DUV) light as the light source, with a wavelength of about 193nm. The wavelength of light limits the smallest feature size (resolution limit) that can be manufactured. As chip technology advances, traditional DUV photolithography increasingly fails to meet the requirements.

This led to the development of EUV (Extreme Ultra-Violet) lithography machines.

EUV photolithography uses extreme ultraviolet light with a wavelength of just 13.5nm, much smaller than DUV, enabling the creation of smaller feature sizes to meet the demands of advanced chip processes (such as 7nm, 5nm, and 3nm).

EUV photolithography requires extremely precise light concentration, with stringent process accuracy. For example, the mirrors used for reflection in an EUV machine are 30cm long, and their surface fluctuation must not exceed 0.3nm. This is equivalent to ensuring that the track from Beijing to Shanghai is perfectly level with a fluctuation no larger than 1mm.

The extremely high technical standards make EUV photolithography machines incredibly difficult to manufacture. Only a few companies globally are capable of developing and manufacturing EUV machines, with the leading player being the renowned Dutch company ASML.

According to ASML, each EUV machine contains 100,000 parts, 40,000 bolts, 3,000 wires, and 2 kilometers of hoses. The majority of parts come from the most advanced products in various countries, such as gratings from the U.S., lenses from Germany, bearings from Sweden, and valves from France.

Each EUV machine costs around 100 million USD and weighs 180 tons. Transporting one requires 40 shipping containers, 20 trucks, and 3 air shipments. Installation and debugging take at least one year.

ASML can only produce a maximum of 30 EUV machines per year, and they are not willing to sell them to us. The most significant “bottleneck” in the entire chip industry is the EUV photolithography machine.

04

█ Etching

Let’s continue with the chip manufacturing process.

At this point, the pattern has appeared, but we have only removed part of the photoresist. What we really need to remove is the underlying oxide layer (the part not protected by photoresist).

In other words, we need to continue “digging.”

The process used here is etching.

Etching can be divided into wet etching and dry etching.

Wet etching involves immersing the wafer in a liquid solution containing specific chemicals, which dissolve the semiconductor structure (oxide layer) that is not protected by photoresist.

Dry etching uses plasma or ion beams to bombard the wafer and remove the unprotected semiconductor structures.

There are two key concepts in etching: isotropy (anisotropy) and selectivity ratio.

Wet etching is isotropic, meaning etching occurs in all directions. Dry etching is anisotropic, meaning etching occurs in the vertical direction. The latter is clearly preferable.

In etching, both the oxide layer and photoresist are etched. The etching rate of photoresist relative to the etched material (oxide layer) is called the selectivity ratio. Clearly, we want to etch as little photoresist as possible and remove more of the oxide layer.

Currently, dry etching dominates the industry and is the preferred choice.

Dry etching offers better fidelity, whereas wet etching is difficult to control, especially in advanced processes like 3nm, where it can reduce line widths or even damage circuits, lowering chip quality.

05

█ Doping (Ion Implantation)

Alright, we’ve covered the “digging” process.

At this point, the wafer’s surface has various trenches and patterns.

Next, let’s look at the doping process.

In the previous photolithography and etching steps, we’ve only created holes. Now, based on these holes, we will form P-wells and N-wells.

Pure silicon itself is non-conductive, so to make it semiconductive, we need to add some impurities (called dopants) to alter its electrical properties.

For example, adding phosphorus, antimony, and arsenic to silicon creates an N-well. Adding boron, aluminum, gallium, and indium creates a P-well.

N-type silicon has free electrons, while P-type silicon has many holes and fewer free electrons. By applying a voltage to the gate in the channel, electrons can be attracted from the P-type material, forming a channel (conductive path). A current then flows between two N-type regions.

This means that in the NPN transistor, prior to oxidation, ion implantation has already been used to dope the substrate with boron (and a small amount of phosphorus), turning it into a P-well substrate. (I haven’t mentioned this step earlier for readability.)

Now, we can do phosphorus doping in the hole areas to form the N-wells.

Did you get it? The purpose of doping is to create P-N junctions and form transistors.

Doping includes two processes: thermal diffusion and ion implantation. Thermal diffusion is not as selective as ion implantation, so ion implantation is currently the preferred method except for specific needs.

Ion implantation uses high-energy particle beams to inject impurities directly into the silicon wafer.

The ion sources are typically gases like phosphine (PH3) or boron trifluoride (BF3). These gases are ionized in a reaction chamber by high-speed electrons, creating ions.

At this point, the ions are analyzed using a mass spectrometer and deflected in a magnetic field to select the ions needed (as different ions have different deflection angles). These ions are then implanted into the wafer.

The silicon dioxide layer (oxide layer) now serves as a blocking layer for ion implantation.

After ion implantation, the wafer needs to be heated to 900°C for annealing.

Annealing helps the implanted dopants diffuse more evenly into the silicon wafer and repair the damage caused by ion implantation, as it disrupts the silicon lattice.

06

█ Thin Film Deposition

We’ve been “digging” so far, but now we start “building.”

You’ll notice that this is a very complex three-dimensional structure. It has many layers, somewhat like a building or a complex traffic network.

At the very bottom of this structure is the silicon substrate we’ve carefully crafted.

As the foundation of the chip building, the substrate must have excellent thermal stability and mechanical properties, and also provide electrical isolation to prevent interference.

On top of the substrate are the transistor body parts, and above that are the core components of the transistor, such as the source, drain, and channel.

The gate of the transistor is mainly made of “polysilicon,” which has good conductivity and stability, making it suitable for controlling the on-off state of the transistor. The metal connections for the source, drain, and gate are typically made of tungsten.

Above that, we need to build many interconnecting “roads” (circuits) to connect these transistors and form complex functional circuits.

For these interconnects, metals like copper are ideal materials. Let’s call this layer the metal interconnect layer.

Since it’s all metal, there’s a risk of short circuits, so insulating layers (films) are needed to isolate the circuits.

At the top of the chip, there is typically an additional passivation layer. The passivation layer mainly serves a protective function, preventing contamination, oxidation, and mechanical damage from the outside environment.

So, how do we build all these layers?

The answer is thin film deposition.

This multi-layer architecture is created through the deposition of thin films (ranging from sub-micron to nanoscale thickness). Some of these are thin metallic films (conductive), while others are dielectric films (insulating). The processes used to create these films are called deposition.

Deposition includes chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

Chemical vapor deposition (CVD) involves chemical reactions to generate solid materials, which are then deposited onto the wafer to form thin films. It is commonly used to deposit insulating films like silicon dioxide and silicon nitride.

CVD comes in many varieties. Plasma-enhanced chemical vapor deposition (PECVD), which was mentioned earlier for oxidation, is an advanced method that uses plasma to generate reactive gases.

This method lowers the reaction temperature, making it ideal for temperature-sensitive structures. Using plasma also reduces the need for multiple deposition cycles, often resulting in higher quality thin films.

Physical vapor deposition (PVD) is a physical process.

In a vacuum, argon ions are accelerated to hit the target material, causing the target atoms to be sputtered and deposited in a snowflake-like pattern on the wafer surface to form a thin film.

PVD is commonly used to deposit metallic thin films for electrical connections.

The process of forming metallic layers (like copper or aluminum) through PVD sputtering or electroplating is known as metallization or metal interconnection.

There are two types of metallization: aluminum interconnects and copper interconnects. Copper has lower resistance and higher reliability (better resistance to electromigration), so it is the mainstream choice today.

Atomic layer deposition (ALD) is a method of depositing materials in single atomic layers on the wafer surface. It involves alternating deposition cycles where each cycle deposits only one atomic layer.

ALD is highly precise, and by controlling the number of cycles, we can precisely control the thickness of the deposited film.

07

█ Cleaning and Polishing

Throughout the processes of photolithography, etching, deposition, and so on, repeated cleaning and polishing are necessary.

Cleaning uses high-purity chemical solutions to remove impurities and contaminants from the wafer’s surface, ensuring the purity of subsequent processes.

Polishing is used to eliminate surface roughness and defects, improving the precision of photolithography and the reliability of metal interconnections, enabling the creation of higher-density, smaller integrated circuit designs and manufacturing.

In the previous issue on wafer preparation, we mentioned CMP (chemical mechanical planarization), a process that combines chemical etching and mechanical polishing to flatten the wafer surface.

Without CMP, the structure would be crooked, and subsequent processes could not proceed, leading to poor-quality chips.

08

█ Repeated Cycles

As mentioned earlier, a chip has dozens or even hundreds of layers.

In reality, each layer is built through a repeated cycle of photolithography, etching, deposition, cleaning, and CMP.

After many cycles, the chip building is finally “topped”! Let’s celebrate!

But don’t get too excited! After the “topping,” there are still many post-processing steps left!

09

█ Probe Testing

After the previous processes, the wafer now contains many small square units called dies.

The term “Die” may sound surprising at first, as it’s not related to the word “death.”

In fact, it has nothing to do with death. “Die” comes from the German word “Drahtzug” (wire drawing process) or from the “diced” action of cutting.

Once the building is topped, the first task is, of course, testing.

Testing is necessary to ensure the semiconductor chip meets the quality standards. Those dies that fail the test will not enter the packaging process, saving both time and cost.

The wafer electrical parameter sorting (EDS) method is used for testing, usually consisting of five steps, as follows:

Step 1: Electrical Parameter Monitoring (EPM).

EPM tests each device (transistor, capacitor, diode) on the chip to ensure its electrical parameters meet standards. The data from EPM tests helps improve process efficiency and product performance (it is not used to detect defective products).

Step 2: Wafer Aging Test.

The wafer is tested at a specific temperature and voltage to identify products that may develop early defects.

Step 3: Probe Testing.

At this stage, the chip has not yet been cut or packaged, and its pads are exposed.

Thus, probe testing involves connecting the chip’s pads to automated testing equipment (ATE) using a precision probe station.

ATE applies preset test signals and checks whether the chip meets the required performance standards such as operating voltage, current consumption, signal timing, and correct execution of specific functions. Probe testing also includes electrical testing (detecting shorts, opens, leakage, etc.) as well as temperature, speed, and motion testing.

Step 4: Repair.

Some defective chips can be repaired by replacing the faulty components.

Step 5: Marking.

Dies that fail the test are marked. In the past, special ink was used to mark defective chips so they could be identified visually. Today, sorting is done automatically based on test data.

After testing, the front-end processes of chip manufacturing are complete. Those who made it this far are true fans!

In the next issue, we will introduce the back-end processes, where the chip is cut, packaged, tested, and shipped out.

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