According to reports, on April 16, local time, the JEDEC Solid State Technology Association announced the official launch of the HBM4 memory specification JESD270-4, which sets higher bandwidth performance standards for the latest version of HBM.
Compared to previous versions, the HBM4 standard has been improved in several areas, including bandwidth, number of channels, power consumption, and capacity.
HBM4 uses a 2048-bit interface with a transmission speed of up to 8Gb/s, allowing the total bandwidth to reach 2TB/s. It also supports 4 / 8 / 12 / 18 layer DRAM stacks and chip densities of 24Gb / 32Gb, with a single stack capacity of up to 64GB.
Additionally, HBM4 doubles the number of independent channels per stack, increasing from 16 channels (HBM3) to 32 channels, with each channel containing 2 pseudo-channels. This provides greater flexibility for designers. In terms of energy efficiency, it supports vendor-specific VDDQ (0.7V, 0.75V, 0.8V, or 0.9V) and VDDC (1.0V or 1.05V) voltage levels, reducing power consumption and improving energy efficiency.
The HBM4 interface definition ensures backward compatibility with existing HBM3 controllers, enabling seamless integration and flexibility across various applications and allowing a single controller to work with both HBM3 and HBM4 when needed.
Barry Wagner, chairman of the JEDEC HBM subcommittee and NVIDIA’s director of technical marketing, stated that high-performance computing platforms are rapidly evolving, requiring innovations in memory bandwidth and capacity. The HBM4 standard is designed to drive leaps in AI and other accelerated applications for efficient, high-performance computing.
Source: JEDEC
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