The purpose of the chip test is to quickly understand its health.
There are tens of thousands of chips in the daily flow of large companies, and the pressure of testing is tremendous. After the Wafer factory makes the chip, it enters the Wafer Test stage. This testing phase may occur in the fab or may be sent to a nearby test vendor for agent execution.
The production engineer will use an automatic test instrument (ATE) to run the program given by the chip designer and roughly divide the chip into good/bad parts. The bad parts will be discarded directly. If there are too many bad chips at this stage, it will be assumed that the wafer factory itself has a low yield. If the yield drops below a certain number, the fab needs to lose money.
After passing the Wafer Test, the Wafer is cut. The cut chips are classified according to the previous results. Only the good chips are sent to the packaging plant for packaging. The location of packaging is usually near the fabs because unpackaged chips cannot be shipped long distances. The type of packaging depends on the needs of the customer, some need spherical BGA, and some need pins, in short, this step is very simple, with fewer failures. Because the success rate of packaging is much greater than the chip production rate, packaging will not be tested.
After packaging, the chips are sent to the companies’ test plants, also known as production plants. In fact, there are more than ten processes in the production plant, and the Final Test is only the first step. After the Final Test, there are still steps to classify, lettering, check the packaging, and packaging. It can then be shipped to market.
Final tests are the focus of the factory and require a lot of machinery and equipment. Its purpose is to classify chips strictly. In the case of Intel SoCs, these phenomena can occur in Final tests:
- Although the Wafer Test was passed, the chip was still bad.
- The package is damaged.
- The chip is partially damaged. For example, the CPU has two cores damaged, the GPU is damaged, or the display interface is damaged
- The chip is good and there is no fault.
At this point, the engineer and the Marketing Department need to decide how to classify these chips. A broken GPU, for example, is considered a Celeron processor with no display core. For example, if you lose two CPUs, consider it a Core i3. The chip works fine, but not very often, as the Core i5 series processor. There’s nothing wrong with it. It’s a Core i7 processor.
What about the Final Tests here?
The final Test can be divided into two steps: 1. Automatic Test equipment (ATE). 2. System-level test (SLT). 2 is required. 1 is generally not available for small companies.
ATE
ATE tests typically take a few seconds, while SLT tests take several hours. The presence of ATE greatly reduces chip testing time.
ATE is responsible for a large number of projects, and there is a strong logical connection. Tests must be carried out in order, and for the first test results, the test items in the following column may be skipped. The contents of these projects are confidential, so I’ll list just a few: For example, power detection, pin DC detection, test logic circuit (generally JTAG) detection, high voltage wafer roasting, PHYSICAL connection layer PHY detection, IP internal detection (including Scan, BIST, Function, etc.), IP IO detection (such as DDR, SATA, PLL, PCI-E, Display, etc.), auxiliary function detection (such as thermodynamic characteristics, fuse, etc.).
These tests give Pass/Fail, and it is the job of the test engineer to analyze the health of the chip based on these passes /Fail.
SLT
SLT is logically simpler. Install the chip on the motherboard, configure the memory, and peripherals, start an operating system, and then test with a software toaster and record the results and compare. Also, detect BIOS-related items.
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