In 2020, the JEDEC Solid State Technology Association first announced the DDR5 SDRAM standard, with a focus on increasing memory density and frequency. It reached a maximum speed of 6400 Mbps, with a maximum capacity of 2TB for a single LRDIMM and 128GB for UDIMM.
Recently, the JEDEC Solid State Technology Association announced the latest JESD79-5C DDR5 SDRAM standard, aimed at enhancing reliability and security, and further boosting performance for various applications ranging from high-performance servers to emerging technologies like artificial intelligence (AI) and machine learning (ML). The new standard is now available for download from the official website.
In the JESD79-5C DDR5 SDRAM standard, JEDEC introduced an innovative solution to improve DRAM data integrity, called PRAC, which accurately calculates DRAM activation counts at the row granularity level. When PRAC-enabled DRAM detects excessive activations, it will alert the system to pause traffic and take mitigating actions within a specified timeframe. This close coordination between DRAM and the system provides a fundamentally accurate and predictable method for addressing data integrity challenges.
Key features of the JESD79-5C DDR5 SDRAM standard include:
- Expanding standard timing parameters from 6800 Mbps to 8800 Mbps
- Extending DRAM core timings and Tx/Rx AC timings to 8800 Mbps, whereas previous versions only supported up to 6400 Mbps timing parameters and up to 7200 Mbps core timings
- Introducing Self-Refresh Exit Clock Sync to optimize I/O training
- Incorporating dual-die package (DDP) timings
- Phasing out Partial Array Self Refresh (PASR) to address security concerns
Mian Quddus, Chairman of the JEDEC Board, expressed his pleasure in the JC-42 Committee’s efforts to advance the DDR5 SDRAM standard, noting that the breakthrough features of JESD79-5C are designed to support the industry’s evolving needs for security, reliability, and performance in various applications.
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