For those of you who care about SSDs, you probably know that the speed of solid-state drives are several times that of ordinary mechanical hard drives, which can effectively improve the speed of computer switching, and also solve the problem of computer lag. Let's see what SSD is? What about the internal structure?
Let’s talk briefly about the development of solid-state drives, and the current market landscape of the solid-state drive industry, and these are relatively big, relatively macro things. Today, we will start from the micro, from the solid-state disk itself, with a simple analysis of the internal and external structure of the SOLID-state disk, so that more people know what the solid-state disk looks like.
▮ What are the differences between HDDs & SSDs?
- Mechanical hard disks use magnetism to record data, similar to the magnetic tape used to listen to music as a child. If we need to find a piece of data, the disk will rotate to the location where the information is recorded, and the magnetic head will sense the magnetism to read the data.
- Solid-State Drives (SSD) are hard disks made of an array of solid-state electronic memory chips. It consists of a control unit, a storage unit (FLASH chip, DRAM chip), and a cache unit. Unlike mechanical hard disks, which consist of mechanical components such as disks and magnetic heads, the entire SSD structure consists of electronic chips and circuit boards instead of mechanical devices. According to the definition of a solid-state drive, we can know the internal structure of a solid-state drive, which actually is composed of three large master chips, flash memory particles, and cache units, so next, let’s look at it one by one.
▮ Nand Flash of Solid State Drive (top priority)
Flash memory, which is used to store data in solid-state drives, is classified as SLC, MLC, and TLC, and are the most important parameters for selecting solid states.
SLC: S is single, as in single dog (unmarried). Therefore, each storage unit of SLC only stores 1bit of data. This storage model is stable, fast in reading and writing, error-free, and has a long life. Therefore, it is also the most expensive. MLC: M stands for multi. Generally, MLC means two. Therefore, each MLC storage unit contains two bits of data. TLC: T is triple, that's right, the "triple kill" of that triple kill!
So, each storage cell of the TLC Nand flash has to squeeze 3 bits of data. (Since MLC stands for multiple bits, including three, some vendors, such as Samsung, refer to their EVO solid-state drives using TLC particles as “3Bit MLC.”)
We think of storage space as a huge parking lot, where each storage unit is a parking space and a bit of data is a car.
SLC Nand Flash: 1bit exclusive parking space, this car to come and go freely, there will be no mistakes, and the speed is very fast, because the parking space use frequency is not high, so the life is very long, but the cost is very high. MLC Nand Flash: 2 bits occupy a parking space, and the entry and exit of 1 car and 2 cars need to be scheduled by the administrator. The efficiency is slightly lower, so the speed will be slower. The parking space usage frequency is doubled, so the service life will be shorter. TLC Nand Flash: 3bit squeeze a parking space, in and out of the scheduling is more complex, lower efficiency, so the speed is slow, but also prone to error, short life.
Although we say that TLC particles have a short life, that is relative to SLC and MLC. After severe tests, TLC particles have had no problem in normal use for more than 5 years. TLC particle SOLID-state disk is also the most common, mainly the SSD particle price is close to the people, the public user enough, so the most common.
▮ The Controller Chip
If the storage space is a large parking lot, then the controller is the “administrator” of this large parking lot. He is responsible for directing every car to enter and exit their parking space accurately and reasonably.
For a parking lot of this size, especially a TLC pellet parking lot with three cars crammed into one space, the caretaker is very worried and tired every day. Therefore, the master “administrator” must have excellent physical quality (hardware) and solid management methods (firmware).
Good controller + excellent firmware is equivalent to letting trained police manage the parking lot, slag and slag controller + firmware is equivalent to letting a gaunt, no education and trained people manage, so, even if you are in the parking lot is solid. Still, before long, the administrator first dead tired, and the whole parking lot also cannot use.
Good master brands are Marvell, SandForce, Samsung, Intel, Toshiba, and so on. In recent years, some of Taiwan’s leading brands, such as SMI and Phison, are also catching up.
When you have a lot of data to store, that is, many cars in the parking lot at once, the controller “administrator” is overwhelmed. But the CPU is very powerful: “I have sent so many cars (data) to you, you work slowly can not let me wait ah! I have so much to do!”
If there is no cache in the temporary parking lot, he will have to wait for the CPU, and we will feel “slow” and “card”, but if we have a cache so a temporary parking lot, the administrator can say, “I’ll spend the rest of the car in the parking lot of the temporary, I am in the busy eyes make arrangements for the car parking Spaces.” So the CPU can happily go about its business, we will feel the computer speed “fast”, “smooth”.
But the downside of caching is that if the hard drive is not protected against a power failure, the car may disappear. (Regular manufacturers will have power protection measures, don’t worry too much)
▮ 3D NAND stack technology
This is a technology that has only become popular in recent years. If you remember the parking lot, it makes sense.
The 3D stack is due to the increasing capacity of solid-state drives in recent years, so the density between the “parking Spaces” of each storage unit is increasing, so we have replaced the ordinary one-story parking lot with many-story parking lots. This way, there is less crowding between each parking space, and the interference changes, so the performance is better. And for manufacturers, the cost is lower.
▮ Interface, bus, protocol
Due to the rapid development of solid-state disks in recent years, new and old products alternate technology, so the solid-state disk interface, protocol, and so on in the market is a bit chaotic, there is a constant cut between them, but fortunately, I have a piece of knowledge to eat down.
A connector is a plug made of several electrically conductive copper wires in different shapes. The mainstream SSD interfaces on the market are SATA, mSATA, M. 2, and PCI-E slots.
In addition to the difference in appearance between them, there are also big differences in performance.
The bus is something we can’t see, can be understood as the data transmission “highway”, SATA bus, and PCI-E bus two kinds.
If we want to drive from CITY P to city Y, taking the PCI-E bus is equivalent to taking a direct highway between the two places, while taking the SATA bus is equivalent to taking a relatively roundabout urban and rural road.
The PCI-E bus has several levels, PCI-E x 1, PCI-E x 2, PCI-E x 4, PCI-E x 8, and PCI-E x 16. The higher the number, the faster the speed. Current solid-state drives are all in the x 2, x 4 grade, which has a maximum speed of 3000 MB/s or more. Speaking of which, there are smart partners who may have thought of the graphics card we use is already x 16 level.
As mentioned above, PCI-E ×4 is a flat highway, but as we all know, in reality, the speed of each car on the highway is also different, and sports cars will always be faster than cars. SSDS with NVMe protocols is the equivalent of supercars designed specifically for this flat highway. In a PCI-e x 4 lane, a hard disk that does not support NVMe can run at most 1500MB/s, while a hard disk that supports NVMe can run at least 3000MB/s.
▮ architecture Model
Single-port PCIe SSD
Dual-port PCIe SSDS with SMBus or I2C
The NVMe management interface is used to send command messages, which consist of standard NVMe management commands targeted at controllers in the NVM subsystem. Commands for accessing the PCI Express configuration, I/O, and storage space of the controllers in the NVM subsystem; And management interface-specific commands for counting, configuring, and monitoring the NVM subsystem.
NVM subsystem associated with single-port PCIe SSDs
The illustration above shows a sample NVM subsystem corresponding to the PCIe SSD shown in Figure 3. The NVM subsystem consists of one controller associated with PCIe port 0 and two controllers associated with PCIe port 1. Management endpoints and SMBus/I2C ports are associated with each PCIe port. Because the NVM subsystem contains management endpoints, all controllers have associated controller management interfaces.
NVM subsystem associated with two-port PCIe SSDS with SMBus/I2C
The management interface request and response messages are transmitted as MCTP messages, and the message type is set to NVM Express management messages via MCTP (see MCTP ID and code specification). All command messages originate from the management controller and a response message is generated from the management endpoint.
Relationship among Clusters, Pages, and Blocks
The disk capacity is calculated based on the following formula: Storage capacity = Number of magnetic heads x number of tracks (cylinders) x Number of sectors x number of bytes per sector
- Sector: the smallest storage unit of a disk;
- Disk block: the smallest unit of reading and writing data in a file system;
- Page: minimum storage unit of memory;
- A disk block consists of consecutive (2^n) sectors;
- The page size is 2^ N times the disk block size;
- Page size: getconf PAGE_SIZE, usually 4K;
- Disk Block size view: the stat/boot / | grep “IO Block”, common for 4 k;
- View the sector size: fdisk -l, which is usually 512 bytes.