It has been more than 20 years since Samsung produced the earliest commercial DDR SDRAM chips in 1998, and the DRAM market has been developing, from DDR to DDR2, DDR3, DDR4, and then to DDR5 which is about to enter the market.
Today we’re going to talk about DDR’s JEDEC specification.
What’s the JEDEC?
Full name of JEDEC: JointElectron Device Engineering Council
JEDEC is a global solid-state technology association that theoretically does not belong to any country or government entity and sets standards for the semiconductor industry.
Including many aspects, today we only focus on the relevant specifications of DDR.
The development of DDR began in 1996, and the specification JESD79 corresponding to JEDEC was released in 2000.
The JEDEC specification consists of two parts, one for a memory chip, and the other for memory module.
Of course, with the rise of RDIMM, LRDIMM, JEDEC correspondingly formulated the specifications of RCD and Data Buffer.
Today we are mainly talking about JEDEC’s SDRAM specification, that is, the JESD79 series. It is important to note that this specification is for DRAM chips, not memory chips.
Interested students can go to the JEDEC website to download the corresponding specification, the last letter of the specification represents the version, such as JESD79-4C C represents the current version of the DDR4 SDRAM specification is C.
The number after JESD79 represents the generation of DDR.
At present, the specification for DDR5 SDRAM on the JEDEC website is still under development, and if it continues to follow this naming rule, it should be JESD79-5.
|Double Date Rate (DDR) SDRAM||JESD79F|
|DDR2 SDRAM Specification||JESD79-2F|
|DDR3 SDRAM Standard||JESD79-3F|
|DDR5: JEDEC DDR5 standard is currently in development||NA|
The following table lists the major changes in the JEDEC specification from DDR to DDR5. We can see that in order to meet the continuous pursuit of performance, capacity and power saving in the industry as a whole, the operating voltage of the specification is getting lower and lower, the chip capacity is getting larger and larger, and the IO rate is getting higher and higher.
Although the JEDEC specification of DDR5 has not been formally introduced, we can draw the same conclusion from this trend and the existing online data.
|Device Width||x4, x8, x16||x4, x8, x16||x4, x4, x16||x4, x8, x16||x4, x8, x16|
|Bank||4||up to 8||8||4 banks|
|2 or 4 banks per group|
|Bank Group||NA||NA||NA||4 for x4/x8; 2 for x16||8 for x4/x8; 4 for x16|
|Burst Length||2,4 or 8||4 or 8||8||8||16|
Disclaimer: at present, the JEDEC standard of DDR5 has not been officially released, so all the data related to DDR5 here come from the data published on the Internet, and the subsequent release of JEDEC shall prevail.
At the same time, starting with DDR5, there are two separate channels on each memory.
From the above table, we can also see that in addition to the changes in voltage, capacity and IO rate, we also list the evolution of Bank, Bank Group, Prefetch, and Burst Length, the number of bank increases more and more, and the number of bank group, prefetch increases from 2n to 4n 8n to the appearance of DDR4.
So is there any connection between these changes?
What will happen to DDR5?
To understand this, we need to review the basic read and write operations of SDRAM, as well as the core frequency and IO frequency of DRAM.
Prefetch and Burst Length
Although we say that the maximum rate of DDR4 is 3200MT / DDR4, this refers to the IO frequency of DDR4, that is, the data transfer rate of the interface between DDR4 and memory controller.
So how does DRAM achieve a relatively low core transmission frequency to meet the increasing demand for high-speed IO transmission rate?
This is achieved by prefetch.
|IO CLK |
It is easy to understand from DDR to DDR3. Prefetch is equivalent to DRAM core building several highways to connect to the outside IO port at the same time to solve the problem that the IO rate is faster than the internal core rate. The multiple relationship between IO data rate and core frequency is prefetch.
So why not continue to add prefetch after adding prefetch, all the way to DDR4?
Because the increase in prefetch corresponds to the corresponding increase in burst length.
How to understand the relationship between prefetch and burst length?
Prefetch is related to the ratio of DRAM core frequency to IO frequency, while the length of burst length is related to the cache line size of CPU.
The length of Burst length may be greater than or equal to prefetch.
But if the length of the prefetch is greater than the length of the burst length, it is possible to waste data because CPU can’t use that much at a time.
Therefore, from DDR3 to DDR4, if we continue to increase the IO rate by increasing prefetch on the premise of keeping the data lane of DDR4 memory at 64, the data fetched by prefetch will be larger than the size of a cache line (512bits), which will bring performance problems to the current CPU system.
So how did DDR4 solve it?
We notice that in Table 1, Bank Group appears in DDR4, which is the secret weapon that DDR4 can continue to increase the speed of IO without changing prefetch.
DDR4 uses the interleave, of Bank group to achieve a further increase in the IO rate on the basis of DDR3.
As you can see from the above 4 images, each bank group has its own global IO, so that the interleaving of the bank group can be used to further solve the problem of mismatch between internal and external speeds.
It is equivalent to continuing to build parallel relatively slow highways on the basis of DDR3 to take the ultra-high-speed one-way streets outside.
When it comes to DDR5, can we continue to use Bank Group’s interleave to achieve the purpose of increasing the IO rate?
If you continue to do so, the effect on the rate increase will be very limited, so when it comes to DDR5, you are still in the direction of increasing prefetch.
DDR5’s prefetch is 16, so how to solve the cache line size problem we mentioned earlier?
DDR5 takes the approach of reducing the number of DIMM data lanes from 64 data lanes to 32 data lanes, thus continuing to maintain the cache line size of 64 Byte.
From the above development history of JEDEC DDR to DDR4, we can see that the evolution of DRAM is based on serving the CPU system architecture, focusing on cost, reducing power consumption, increasing capacity, and increasing IO rate.
Based on the principle of DRAM operation, maximize the utilization of DRAM.
Therefore, we can also see that DDR5 provides more bank and finer refresh granularity, and so on, all of which are to make the best use of things and improve system performance.
In future articles, we will continue to introduce the basic features of DRAM and the new features of DDR5
Finally, the question left to you is whether it is tCCD_L or tCCD_S between bank group and group based on DDR4. Why?
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