April 1 news, according to the Semiconductor Engineering report, Samsung Electronics announced at the industry conference Memcon 2024 that it plans to be the first in the industry to enter the 3D DRAM memory era after 2025.
The DRAM memory industry will compress the line width to below 10nm later this decade. At such a fine scale, the existing design solutions are difficult to further expand, and the industry is therefore exploring a variety of innovative memory designs including 3D DRAM.
At Memcon 2024, Samsung displayed two new 3D DRAM memory technologies on their slides, including Vertical Channel Transistor and Stacked DRAM.
Compared to traditional transistor structures, the Vertical Channel Transistor changes the channel direction from horizontal to vertical, which can significantly reduce the device area occupation but requires higher precision in the etching process.
Compared to the existing 2D DRAM structure, Stacked DRAM can fully utilize the z-direction space, accommodating more storage units in a smaller area, with single-chip capacity increased to over 100G.
The 3D DRAM market is expected to reach $100 billion by 2028 (note by DiskMFR: currently about 724 billion CNY). To compete with other major memory manufacturers, Samsung has already opened a new 3D DRAM R&D lab in Silicon Valley earlier this year.
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