Q1: What is PIE? What is the main job of PIE?
Answer:
The Process Integration Engineer (PIE), the main job is to integrate resources from various departments, continuously improve processes, and ensure stable and good product yield.
Q2: What does 200mm and 300mm Wafer represent?
Answer:
An 8-inch silicon wafer has a diameter of 200mm, and a 12-inch silicon wafer has a diameter of 300mm.
Q3: What wafer process size is currently used in the three existing SMIC (Semiconductor Manufacturing International Corporation) factories, and what wafer process size will be used in the future Beijing Fab4 (Factory 4)?
Answer:
Currently, Factories 1-3 use 200mm (8-inch) wafers with a process size of 0.13um. In the future, Beijing Factory will use 300mm (12-inch) wafers.
Q4: Why do we need 300mm wafers?
Answer:
Increasing wafer size allows for more chips to be produced on a single wafer, resulting in lower unit costs. Going from 200mm to 300mm increases the area by 2.25 times and the number of chips by approximately 2.5 times.
Q5: What does the term “0.13um technology capability” mean?
Answer:
It means that the factory’s technology capability can achieve a gate line width of 0.13um. When the gate width is reduced, the entire device can become smaller and operate faster.
Q6: What does the change from 0.35um to 0.25um to 0.18um to 0.15um to 0.13um in technology represent?
Answer:
The reduction in gate line width (the size of this dimension represents the level of semiconductor technology) indicates an increase in the difficulty of the manufacturing process at each stage from 0.35um to 0.25um to 0.18um to 0.15um to 0.13um.
Q7: Typically, silicon wafer substrates can be classified into two types, N and P. What do N and P-type wafers mean?
Answer:
An N-type wafer refers to a silicon wafer doped with negative elements (5-valence charge elements, e.g., P, As), while a P-type wafer refers to a silicon wafer doped with positive elements (3-valence charge elements, e.g., B, In).
Q8: What are the main process modules in the manufacturing of silicon wafers in a factory?
Answer:
There are four main modules: DIFF (Diffusion), TF (Thin Film), PHOTO (Photolithography), and ETCH (Etching). The DIFF module includes FURNACE (Furnace Tube), WET (Wet Etch), IMP (Ion Implantation), and RTP (Rapid Thermal Processing). The TF module includes PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), and CMP (Chemical Mechanical Polishing). Silicon wafer manufacturing involves the repetitive production of wafers across different process modules according to customer requirements, and final electrical testing is performed to ensure product quality.
Q9: The manufacturing of silicon wafers is often represented by the notation of “XPYM” and the number of mask layers. What do “XPYM” and the number of mask layers signify?
Answer:
“XPYM” represents the number of Poly (polycrystalline silicon) layers and Metal (metal wiring layers) in the silicon wafer manufacturing process. For example, a 0.15um logic product might be represented as “1P6M” (1 layer of Poly and 6 layers of metal). The number of mask layers indicates how many times the wafer manufacturing process requires photolithography steps.
Q10: The first step in the wafer backend process involves the formation of a start oxide and a zero layer. What is the purpose of the start oxide?
Answer:
The start oxide serves two main purposes:
- It prevents direct contact of organic photoresists with the silicon surface.
- It helps avoid contamination from dust and particles during laser marking processes.
Q11: Why is the zero layer needed?
Answer:
The semiconductor chip’s manufacturing process involves the stacking of many different layers. The zero layer serves as a reference point for alignment between these various layers.
Q12: What is the purpose of Laser marks, and what does Wafer ID signify?
Answer:
A laser mark is used to engrave the Wafer ID. The Wafer ID functions as an identification, similar to an ID card for the silicon wafer, representing the unique identity of each wafer.
Q13: What are the main components of the silicon wafer manufacturing process?
Answer:
- Frontend – The process of manufacturing semiconductor devices.
- Backend – The connection of metal wires and the application of a protective passivation layer.
Q14: What are the key segments of the frontend process?
Answer:
- Formation of STI (Shallow Trench Isolation) for defining active areas and isolating devices.
- Well, an implant for adjusting electrical characteristics.
- Formation of poly gates.
- Formation of source/drain regions.
- Formation of salicide (self-aligned silicide) layers.
Q15: What does STI stand for, and why is STI necessary?
Answer:
STI stands for Shallow Trench Isolation. STI is required to serve as a barrier between two components (devices) to prevent short circuits between them.
Q16: What does AA stand for, and briefly explain its purpose?
Answer:
AA stands for Active Area, which is the region where the main components of a transistor are established, including the source, drain, and gate. The space between two Active Areas is isolated using STI (Shallow Trench Isolation).
Q17: In the etching process of STI, what are the key process parameters to consider?
Answer:
The critical process parameters to consider during STI etching are:
- STI etch angle.
- STI etch depth.
- Control of the critical dimension (CD) size after STI etching.
(CD control, where CD stands for critical dimension)
Q18: In the formation of STI, there is a liner oxide layer. What is the purpose of the liner oxide layer?
Answer:
The liner oxide is an oxide layer formed at 1100°C for 120 minutes in a high-temperature furnace. Its functions are:
- Repairing any substrate damage caused by STI etching.
- Rounding the sharp edges created by STI etching (corner rounding).
Q19: Adjusting the electrical characteristics through well implantation typically involves three steps. What are these steps, and what is their function?
Answer:
Adjusting electrical characteristics through well implantation involves the following three steps:
- Well Implant: Forming N and P well regions.
- Channel Implant: Preventing leakage between source and drain regions.
- Vt Implant: Adjusting the threshold voltage (Vt).
Q20: The manufacturing process for ion implantation layers can be divided into several steps. What are these steps?
Answer:
The manufacturing process for ion implantation layers generally includes the following steps:
- Photolithography (Photo) and pattern formation.
- Ion implantation for adjustment.
- Ashing (plasma cleaning) after ion implantation.
- Photoresist (PR) removal.
Q21: What are the general steps in the formation of Poly (polycrystalline silicon) gates?
Answer:
- Deposition of Gate oxide.
- Deposition of Poly film and SiON (used as an anti-reflective layer in lithography).
- Formation of Poly patterns (Photo).
- Etching of Poly and SiON.
- Ashing (plasma cleaning) and photoresist removal (PR strip) after etching.
- Re-oxidation of Poly.
Q22: What should be considered in the etching (etch) of Poly (polycrystalline silicon) gates?
Answer:
- Control of Poly’s critical dimension (CD) size.
- Avoiding the etching of Gate oxide to prevent damage to the substrate.
Q23: What is Gate oxide?
Answer:
The gate oxide is used as the dielectric layer for devices. By using gate oxide of different thicknesses, the gate voltage can be adjusted for switching different devices.
Q24: What are the steps in the formation of source/drain (S/D) regions?
Answer:
- Implantation (Implant) of Lightly Doped Drain (LDD).
- Formation of spacers.
- High-concentration N+/P+ implantation for source/drain (S/D) regions and Rapid Thermal Anneal (RTA).
Q25: What does LDD stand for, and what is its purpose?
Answer:
LDD stands for Lightly Doped Drain. LDD is a process that uses a lower concentration of source/drain doping to prevent the hot carrier effect in semiconductor components.
Q26: What is the Hot carrier effect?
Answer:
The Hot carrier effect occurs when the electric field between the source and drain regions in a semiconductor device becomes very high due to the small dimensions (typically below 0.5um). This high electric field accelerates charge carriers, causing them to gain energy and become “hot.” These hot carriers can damage the gate oxide and lead to device degradation.
Q27: What is a Spacer, and what should be considered during Spacer etching?
Answer:
A Spacer is a side wall formed on both sides of the gate (Poly) using dielectric materials, typically composed of Ox/SiN/Ox layers. During Spacer etching, it’s important to consider the critical dimension (CD) size, profile, and thickness of the remaining oxide.
Q28: What is the primary function of Spacers?
Answer:
The main functions of Spacers are:
- Creating a lightly doped drain (LDD) region between the high-concentration source/drain regions and the gate.
- Serving as a protective layer for the gate during Contact Etch.
Q29: Why is a thermal anneal process required after ion implantation?
Answer:
Thermal annealing is necessary for several reasons:
- To repair surface damage caused by ion implantation.
- To facilitate the diffusion of implanted ions to the appropriate depth.
- To ensure that the implanted ions occupy the correct lattice positions within the crystal.
Q30: What does SAB stand for, and what is its purpose?
Answer:
SAB stands for Salicide block. Its purpose is to protect the silicon wafer’s surface. Under the protection of the RPO (Resist Protect Oxide), the silicon wafer is shielded from forming silicide with other materials like Ti and Co.
Q31: What should be considered in the process layers of the SAB (Salicide block) process?
Answer:
- After SAB photolithography (photo) and etching (etch), ensure that the pattern, especially in small areas, is fully covered where necessary.
- The thickness of the remaining oxide.
Q32: What is Salicide?
Answer:
Salicide refers to the formation of a compound, such as TiSix or CoSix, where silicon (Si) combines with materials like titanium (Ti) or cobalt (Co). It is primarily used to reduce contact resistance values (Rs, Rc).
Q33: What are the main steps in the formation of Salicide?
Answer:
- Deposition of Co (or Ti) and TiN.
- First Rapid Thermal Anneal (RTA) to form Salicide.
- Removal of unreacted Co (Ti) using chemical acids.
- Second RTA (used to transform Ti to a crystalline phase, reducing its resistance).
Q34: What are the main characteristics of MOS (Metal-Oxide-Semiconductor) devices?
Answer:
The main characteristic of MOS devices is their ability to control the current between the source and drain (I_ds) by adjusting the gate voltage (V_g), thereby achieving switching behavior.
Q35: Which parameters are typically used to evaluate the characteristics of a device?
Answer:
The key parameters used to evaluate device characteristics are:
- I_dsat: Saturation drain current.
- I_off: Off-state current.
- Vt: Threshold voltage.
- Vbk (breakdown): Breakdown voltage.
- Rs: Source resistance.
- Rc: Contact resistance.
Typically, higher I_dsat and Vbk values are desirable, while lower I_off and Rc values are preferred. Vt and Rs should be as close to the design values as possible.
Q36: What is Idsat, and what does Idsat signify?
Answer:
Idsat stands for Saturation Drain Current. It represents the maximum current flowing between the source and drain when the gate voltage (Vg) is at a constant level.
Q37: Which process steps during fabrication can affect Idsat?
Answer:
Idsat can be influenced by various process parameters, including Poly CD (polycrystalline silicon size), Gate oxide thickness (Gate oxide Thk), Active Area (AA) width, Vt implantation conditions, LDD implantation conditions, and N+/P+ implantation conditions.
Q38: What is Vt, and what does Vt signify?
Answer:
Vt stands for Threshold Voltage. It is the minimum voltage required to induce strong inversion. When the gate voltage (Vg) is less than Vt, the MOS device is in the off state, and when Vg is greater than or equal to Vt, it creates a conducting channel between the source and drain, and the MOS device is in the on state.
Q39: Which process steps during fabrication can affect Vt?
Answer:
Vt can be influenced by process parameters such as Poly CD, Gate oxide thickness (Gate oxide Thk), Active Area (AA) width, and Vt implantation conditions.
Q40: What is Ioff, and why is it beneficial for Ioff to be small?
Answer:
Ioff represents the off-state current, which is the current between the source and drain when Vg is equal to 0. Smaller Ioff values are desirable because they indicate better gate control, reducing unnecessary leakage currents and improving power efficiency.
Q41: What is device breakdown voltage?
Answer:
Device breakdown voltage, also known as breakdown voltage or breakdown voltage of a device, refers to the maximum voltage that Vd (drain voltage) can withstand when Vg (gate voltage) and Vs (source voltage) are both equal to 0. When Vd exceeds this voltage, it causes the formation of a conductive channel between the source and drain, independent of the gate voltage. As devices become smaller, this phenomenon becomes more critical.
Q42: What are ILD and IMD, and what is their purpose?
Answer:
ILD stands for Inter-Layer Dielectric, which is used to isolate devices from the first metal layer. IMD stands for Inter Metal Dielectric, used to isolate different metal layers from each other. The purpose of ILD and IMD is to provide insulation and prevent electrical interference between different device layers and metal layers. It’s essential to control the thickness of ILD and IMD after chemical mechanical polishing (CMP).
Q43: What are the typical layers involved in the formation of ILD (Inter-Layer Dielectric)?
Answer:
The formation of ILD typically involves the following layers:
- Deposition of SiON layer (to prevent the diffusion of B and P from upper layers into the device).
- Deposition of BPSG (Boron and Phosphorus-doped Silicon Glass) layer.
- Deposition of PETEOS (Plasma Enhanced Tetraethyl Orthosilicate) layer. These layers are subsequently chemically mechanically polished (CMP) to achieve planarization.
Q44: What are the typical layers involved in the formation of IMD (Inter Metal Dielectric)?
Answer:
The formation of IMD typically involves the following layers:
- Deposition of the SRO (Silicon Rich Oxide) layer (to prevent the diffusion of fluorine ions from upper layers into the device).
- Deposition of HDP-FSG (High-Density Plasma Fluorinated Silicon Glass) layer.
- Deposition of PE-FSG (Plasma Enhanced Fluorinated Silicon Glass) layer. The purpose of using FSG is to reduce the dielectric constant (k-value) and minimize parasitic capacitance between metal layers. These layers are subsequently chemically mechanically polished (CMP) for planarization.
Q45: Briefly explain the steps involved in the formation of Contacts (CT).
Answer:
The formation of Contacts involves the following steps:
- Photolithography for Contacts (CT).
- Etching of Contacts and removal of photoresist (ash & PR strip).
- Deposition of a glue layer.
- Deposition of CVD W (Chemical Vapor Deposition of Tungsten).
- Chemical Mechanical Polishing (W-CMP) to achieve planarization. Contacts are used to establish connections between devices and metal lines and are distributed on poly and Active Areas (AA).
Q46: Where is the glue layer deposited, and what are its composition and deposition methods?
Answer:
The glue layer is primarily deposited between the Salicide and W (CT) or between W (VIA) and metal to enhance adhesion. It is composed of Ti and TiN, and it is typically fabricated using PVD (Physical Vapor Deposition) and CVD (Chemical Vapor Deposition) methods.
Q47: Why are CVD W-plugs (Chemical Vapor Deposition of Tungsten plugs) commonly used for connections between metal layers?
Answer:
CVD W-plugs are commonly used because of their low resistance and excellent step coverage. They provide a reliable and efficient way to connect different metal layers within the semiconductor device.
Q48: What is the typical method used for the formation of metal layers, and what are the general steps involved?
Answer:
The typical method used for the formation of metal layers is PVD (Physical Vapor Deposition) of the metal film. The general steps involved are as follows:
- Deposition of the metal film using PVD.
- Photolithography (Photo) for defining the metal patterns.
- Metal film etching and plasma cleaning (usually carried out sequentially in the same equipment to prevent metal corrosion).
- Removal of photoresist using solvent.
Q49: How do the thickness and line width of Top metal differ from Inter metal?
Answer:
Top metal is typically much thicker than Intermetal. In a 0.18µm process, Inter metal may be 4KA (4,000 Angstroms), while Top metal can be 8KA (8,000 Angstroms) or thicker. This is because Top metal often carries a higher current load and requires greater thickness to reduce resistance. Additionally, the line width of the Top metal is generally wider than Intermetal.
Q50: When evaluating the quality of contact/via openings, which electrical parameter is used to assess it?
Answer:
The quality of contact/via openings is typically evaluated using the parameter Rc (contact resistance). A lower Rc value indicates better contact quality and lower resistance in the contact or via.
Q51: What is Rc, and what does it represent?
Answer:
Rc stands for contact resistance. It represents the resistance formed at the point of contact between metal and semiconductor (contact) or between two metal layers (via). Lower Rc values indicate better contact quality and lower electrical resistance.
Q52: What are the primary factors that can affect Contact (CT) Rc?
Answer:
The primary factors that can affect Contact (CT) Rc include:
- Abnormal thickness of ILD CMP (Inter Layer Dielectric Chemical Mechanical Polishing).
- CD (critical dimension) of the contact.
- The proper etching process of the contact.
- Quality or concentration of the contact substrate (Salicide or non-Salicide).
- Formation of the glue layer in the contact.
- The quality of the W-plug in the contact.
Q53: When measuring the characteristics of Poly/metal interconnects, which electrical parameter is used?
Answer:
For measuring the characteristics of Poly/metal interconnects, spacing and Rs values are used to assess the conduction quality and to check for any anomalies in the wires.
Q54: What is spacing, and how is it measured?
Answer:
Spacing, in electrical measurements, refers to the measurement of the current flowing in an adjacent but non-intersecting line when a specific voltage is applied to one line (Poly or metal). Smaller spacing indicates better isolation between the lines, while larger spacing can indicate possible shorts or crosstalk issues. It is measured by applying a voltage to one line and measuring the current in an adjacent line.
Q55: What is Rs?
Answer:
Rs is the sheet resistance, representing the resistance per unit area or length of a material. It is used to measure the electrical conductivity of different regions in a semiconductor device, including AA (N+, P+), poly, and metal layers.
Q56: What are the process factors that can influence Rs?
Answer:
The process factors that can influence Rs (sheet resistance) include:
- The size (critical dimension) of the conductive lines (AA, poly, and metal).
- The thickness of the conductive lines (poly and metal).
- The intrinsic conductivity of the conductive lines (AA, poly, and metal), can be influenced by factors such as ion implantation in the case of AA and polylines.
Q57: What are the three layers typically found in a passivation layer structure?
Answer:
The three layers typically found in a passivation layer structure are:
- HDP Oxide (High-Density Plasma Oxide)
- SRO Oxide (Silicon-Rich Oxygen Oxide)
- SiN Oxide (Silicon Nitride Oxide)
Q58: What is the function of a passivation layer?
Answer:
The passivation layer, composed of oxides (e.g., HDP oxide, SRO oxide) and silicon nitride (SiN), serves to protect the underlying layers of the semiconductor device. It acts as a barrier to prevent the contact of these layers with moisture, air, or external contaminants, thereby preventing damage to the circuits.
Q59: What is the purpose of alloying?
Answer:
Alloying is a process used to achieve two main objectives:
- To relieve stress between different layers, ensuring good contact between them.
- To reduce the resistance at the contact interfaces between layers.
Q60: What is the purpose of the WAT (Wafer Acceptance Test) step in the semiconductor manufacturing process?
Answer:
The WAT (Wafer Acceptance Test) is conducted after the semiconductor manufacturing process is completed. Its purpose is to evaluate the electrical performance and characteristics of the fabricated chips, including Idsat, Ioff, Vt, Vbk (breakdown), Rs, and Rc. It serves as a final quality control step to ensure that the fabricated chips meet the specified standards and specifications.
Q61: What are the main items tested during the WAT (Wafer Acceptance Test)?
Answer:
The main items tested during the WAT (Wafer Acceptance Test) typically include:
- Device characteristics testing.
- Contact resistance (Rc) measurement.
- Sheet resistance (Rs) measurement.
- Breakdown voltage testing.
- Capacitance testing.
- Isolation (spacing) testing.
Q62: What is the WAT Watch system, and what is its function?
Answer:
The WAT Watch system is a tool that provides Process Integration Engineering (PIE) engineers with the ability to set different pass/fail criteria for various WAT test parameters and to issue warning alerts. It helps PIE engineers identify process issues early by monitoring the electrical test results.
Q63: What is PCM SPEC?
Answer:
PCM SPEC stands for Process Control Monitor Specification. In a broad sense, it refers to the specifications for all the process measurement parameters during the chip manufacturing process. In a narrow sense, it refers to the specifications for the WAT (Wafer Acceptance Test) parameters.
Q64: How should anomalies detected during WAT measurement be handled?
Answer:
When anomalies are detected during WAT measurement, the following steps are typically taken:
- Check if the WAT test equipment is functioning correctly. Retest if there are equipment issues.
- Perform a double confirmation using manual test equipment.
- Review the product for any recorded process anomalies during manufacturing.
- Perform a cross-sectional inspection (slicing and examination of the product).
Q65: What is EN, and what is its function or purpose?
Answer:
EN stands for Engineering Note. It is a document issued by the CE (Customer Engineering) department and contains detailed information about a specific product, including Technology ID, Reticle, and various specifications and requirements such as HOLD, SPLIT, BANK, RUN TO COMPLETE, PACKAGE, etc. EN provides critical information that enables the establishment of a process flow and guides actions related to the specific product.
Q66: What are the five things that a PIE (Process Integration Engineering) engineer needs to check when coming to the company every day (daily checklist)?
Answer:
The five things a PIE engineer typically checks when coming to the company every day are:
- Check the MES system to review lot statuses.
- Handle in-line hold lots related to defects, process issues, and WAT.
- Analyze and compile in-line raw data and SPC data for relevant products.
- Summarize CP (Critical Parameter) test results for related products.
- Attend the morning meeting and report relevant product information.
Q67: What are the five things that a WAT (Wafer Acceptance Test) engineer needs to check when coming to the company every day (daily checklist)?
Answer:
The five things a WAT engineer typically checks when coming to the company every day (daily checklist) are:
- Check the status of the WAT test equipment.
- Check and handle any WAT hold lots.
- Review retest wafers and test results from the previous day for any anomalies.
- Check if there are new products scheduled for WAT testing.
- Address any handover or transition-related matters.
Q68: What are the five things that a BR (Business Relations) engineer needs to check when coming to the company every day (daily checklist)?
Answer:
The five things a BR engineer typically checks when coming to the company every day (daily checklist) are:
- Review pass-down information and updates.
- Review the status of urgent cases.
- Check for MES (Manufacturing Execution System) issues reported by module and line engineers.
- Review documentation related to the business and ongoing tasks.
- Review the status of various tasks and assignments.
Q69: What does ROM stand for?
Answer:
ROM stands for Read-Only Memory.
Q70: What is YE (Yield Enhancement)?
Answer:
YE stands for Yield Enhancement, which involves processes and efforts to improve the yield or production efficiency in semiconductor manufacturing.
Q71: What role does YE play in an FAB (semiconductor fabrication facility)?
Answer:
YE in a semiconductor FAB involves tracking the causes of defects in the manufacturing process, collecting and analyzing data, and assessing areas for improvement. YE engineers work closely with relevant engineering departments to propose improvement solutions and evaluate their effectiveness.
Q72: What are the primary responsibilities of a YE engineer?
Answer:
The primary responsibilities of a Yield Enhancement (YE) engineer include:
- Reducing excursion or addressing sudden abnormal events in the manufacturing process.
- Improving baseline defect levels in regular manufacturing processes.
Q73: How can excursion reduction be achieved?
Answer:
Excursion reduction can be achieved by effectively monitoring the status of various production tools and processes, identifying the root causes of abnormal defect levels, taking prompt corrective actions, and implementing preventative measures to avoid recurrence.
Q74: How can baseline defect improvement be achieved?
Answer:
Baseline defect improvement involves analyzing product failures, monitoring online defect data, and identifying specific areas for improvement. Continuous efforts are made to drive defect reduction, lower defect levels, and enhance product yield stability.
Q75: What are the main tasks of a YE (Yield Enhancement) engineer?
Answer:
The main tasks of a Yield Enhancement (YE) engineer include:
- Investigating and analyzing abnormal defect incidents during the production process and driving improvement actions.
- Evaluating and establishing defect monitoring and analysis systems.
- Developing and implementing effective defect engineering systems to enhance defect analysis and improvement capabilities.
- Assisting various modules in establishing offline defect monitoring systems for a more effective response to production tool conditions.
Q76: What is a Defect?
Answer:
Defects refer to tangible impurities and imperfections present on a wafer, including:
- Physical foreign materials on the wafer (e.g., micro-dust, process residues, abnormal reaction by-products).
- Chemical contamination (e.g., residues of chemicals and organic solvents).
- Pattern defects (e.g., anomalies resulting from photo or etching processes, mechanical scratches, deformations, uneven film thickness causing color anomalies).
- Crystal lattice defects inherent to the wafer or introduced during the manufacturing process.
Q77: What are the Sources of Defects?
Answer:
Defects can originate from various sources, including:
- Raw materials: This includes wafers, gases, deionized water, and chemicals.
- External environment: Cleanrooms, transport systems, and procedures.
- Personnel: Operators wearing cleanroom attire and gloves.
- Aging of equipment components and by-products produced during the manufacturing process.
Q78: How can Defects be Classified Based on Their Distribution on a Wafer?
Answer:
Defects can be classified based on their distribution as:
- Random Defects: These defects are scattered randomly across the wafer.
- Cluster Defects: Cluster defects are concentrated in specific areas of the wafer.
- Repeating Defects: These defects occur repeatedly in the same area.
Q79: How can Defects be Classified Based on Their Impact on Yield?
Answer:
Defects can be classified based on their impact on yield as:
- Killer Defect: Killer defects have a significant impact on yield.
- Non-Killer Defect: Non-killer defects do not significantly affect yield.
- Nuisance Defect: Nuisance defects, such as those caused by color anomalies or film grain, also do not impact yield.
Q80: What is the General Workflow of Yield Enhancement (YE)?
Answer:
The general workflow of Yield Enhancement (YE) includes the following steps:
- Inspection Tool Scanning of Wafers.
- Transmitting Defect Data to the Yield Management System (YMS).
- Checking if the increase in defect count exceeds the specifications.
- If the defect count exceeds specifications, wafers are sent to a review station for a more detailed examination.
- Confirming the source of defects and notifying the relevant departments to address the issues.
Q81: What Methods are Used by YE to Identify Defects?
Answer:
Yield Enhancement (YE) uses defect inspection tools that scan wafers and identify defects through image comparison. These tools produce defect result files that contain defect-related data.
Q82: What Information is Included in Defect Result Files?
Answer:
Defect result files typically include the following information:
- Defect size.
- Location and coordinates of the defects.
- A defect map indicating the positions of defects on the wafer.
Q83: What are the Types of Defect Inspection Tools?
Answer:
Defect inspection tools come in two main types:
- Bright Field
- Dark Field
Q84: What is Bright Field?
Answer:
Bright-field defect inspection tools receive and process reflected light signals to identify defects on wafers.
Q85: What is Dark Field?
Answer:
Dark field defect inspection tools receive and process scattered light signals to identify defects on wafers.
Q86: Which of the Bright Field and Dark Field has a faster scanning speed?
Answer:
Dark Field
Q87: Which of the Bright Field and Dark Field has better sensitivity?
Answer:
Bright Field
Q88: What are the types of Review Tools?
Answer:
Review tools include Optical Review Tools and SEM Review Tools.
Q89: What is an Optical Review Tool?
Answer:
An optical review tool is an optical microscope that receives optical signals. It has a lower resolution but is faster and more user-friendly.
Q90: What is an SEM Review Tool?
Answer:
An SEM (Scanning Electron Microscope) review tool is used to receive electron signals. It provides higher resolution but is slower. It can analyze the composition of defects and allows for the rotation or tilting of defects for analysis.
Q91: What is the purpose of a Review Station?
Answer:
A review station is used to classify and analyze defects that have been scanned by an inspection tool. It helps in identifying the source of defects.
Q92: What does YMS stand for?
Answer:
YMS stands for Yield Management System.
Q93: What are the functions of YMS?
Answer:
The functions of the Yield Management System (YMS) include:
- Transmitting defect result files generated by inspection tools to review stations.
- Collecting classified defect data from review stations.
- Storing defect images.
Q94: What is a Sampling Plan?
Answer:
A sampling plan defines the sampling frequency and includes:
- Which sites to scan?
- How often to scan 1 lot out of every certain number of lots?
- How many wafers to scan for each lot?
- How many regions to scan on each wafer?
Q95: How is it decided which products need to be scanned?
Answer:
The products selected for scanning are typically those that represent the current state-of-the-art technology and products with a continuous high volume of orders.
Q96: What are the considerations for selecting monitoring sites?
Answer:
The considerations for selecting monitoring sites include:
- Zone Partition: Sites should not be too far apart in terms of process steps, following the concept of zone partitioning.
- Yield Loss Analysis: Identify sites with the most significant impact on yield loss.
- Sites Suitable for Online Defect Analysis: Choose sites where online defect analysis can be easily performed.
Q97: What is Zone Partition?
Answer:
Zone partition is the division of a process into multiple sections or zones to facilitate the identification of the sources of defects.
Q98: How is Zone Partition done?
Answer:
Zone partition is accomplished through the following steps:
- Use existing data to make an initial assessment of the distribution of defects in different process areas.
- Analyze existing defect data and defect review records to identify sites where abnormal defects occur.
- Conduct engineering experiments to pinpoint the exact site or tool responsible for defect occurrence with a finer level of zone partitioning.
Q99: What is yield loss analysis?
Answer:
Yield loss analysis involves collecting and analyzing the impact of defects occurring in different process areas on product yield to determine potential pathways for yield improvement.
Q100: What is the function of yield loss analysis?
Answer:
The main functions of yield loss analysis are:
- Identifying the process steps with the most significant impact on yield.
- Calculating the killing ratio to determine the most critical defect types affecting yield.
- Evaluating the highest achievable yield at the current stage.
Q101: How is the killing ratio calculated?
Answer:
The killing ratio is calculated by performing calculations and analyses using defect maps and yield maps, resulting in a quantitative measure of the impact of a specific defect type on yield.
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