Top Mistakes Electronics Engineers Must Sidestep Today

Misconception 1: Cost Saving

• Common Mistake 1: What color should the indicator light on the panel be? I prefer blue, so let’s choose it.

  Correction: For indicator lights available in the market, colors like red, green, yellow, and orange, regardless of size (below 5mm), packaging, etc., have been mature for decades, so their prices are generally below 50 cents. However, blue indicator lights were invented only in the last three to four years. Their technological maturity and supply stability are relatively poor, hence the price is about four to five times more expensive. If your panel design doesn’t have any special requirements for indicator light color, then avoid choosing blue. Currently, blue indicator lights are generally only used when other colors cannot be substituted, such as displaying video signals, etc.

• Common Mistake 2: There seems to be no significant difference in the size of resistors that are pulled down/pulled up. Let’s just choose an integer 5K.

  Correction: In reality, there is no 5K resistor value in the market. The closest values are 4.99K (1% accuracy) followed by 5.1K (5% accuracy). The cost prices are respectively four times and two times higher than a 20% accuracy 4.7K resistor. 20% accuracy resistors are available only in values like 1, 1.5, 2.2, 3.3, 4.7, and 6.8 (including multiples of 10). Similarly, 20% accuracy capacitors are also limited to these values. For both resistors and capacitors, selecting values outside of these few options necessitates using higher accuracy, leading to several times increased costs. Besides, the quality of resistors is crucial. Sometimes, a batch of low-quality resistors is enough to ruin a project. It’s recommended to purchase from reputable self-operated stores like Lichuang Mall.

• Common Mistake 3: It’s feasible to use 74XX gate circuits for this logic, but it seems outdated. Let’s use CPLD; it looks much more high-end.

  Correction: 74XX gate circuits cost only a few cents, while CPLDs cost at least tens of yuan (although GAL/PAL is only a few yuan, it’s not recommended). This not only significantly increases costs but also adds several times more work in production, documentation, etc. Given that it doesn’t affect performance, using the more cost-effective 74XX is more suitable.

• Common Mistake 4: The PCB design for this board doesn’t require high demands, so let’s use thinner lines and an automatic layout.

  Correction: Automatic routing inevitably occupies a larger PCB area and generates many more vias compared to manual routing. In large-volume products, PCB manufacturers consider line width and the number of vias as important pricing factors, which directly impact the finished PCB yield and drill bit consumption. Additionally, the PCB’s area is also a factor influencing the price. Therefore, automatic routing will inevitably increase the production cost of the circuit board.

• Common Mistake 5: Our system has high requirements, including selecting the fastest MEM, CPU, FPGA, and all other chips.

  Correction: Not every part operates at high speed in a high-speed system. As the speed of components increases, the price almost doubles, and it brings significant negative impacts on signal integrity. Hence, when choosing chips, consideration should be based on the usage level of different parts, rather than using only the fastest ones.

• Common Mistake 6: Stability is sufficient for the program; having longer code and lower efficiency is not critical.

  Correction: CPU speed and memory space come at a cost. If spending a few extra days to enhance program efficiency during coding, it’s cost-effective considering the savings from reducing CPU frequency and memory capacity. The same applies to CPLD/FPGA designs.

Misconception 2: Reliability Design

• Common Mistake 7: This single board has undergone small-scale production, and after extensive testing over a long period, no issues have been found, so there’s no need to review the chip manually.

  Correction: Hardware design and chip applications must comply with relevant specifications, especially all parameters mentioned in the chip manual (voltage resistance, I/O voltage range, current, timing, temperature, PCB wiring, power supply quality, etc.). They must strictly adhere to the settings and cannot rely solely on experiments for verification. Many companies have faced painful lessons where products were sold for one or two years, and when the IC manufacturer changed the production line, the boards ceased functioning. The reason is slight changes in chip parameters within manual limits. If you follow the manual, any changes won’t pose a threat. If parameters go beyond the manual’s range, you can claim compensation (assuming your board still functions, which enhances its reliability).

• Common Mistake 8: I can’t be blamed if problems arise due to user-operating errors.

  Correction: It’s correct to demand strict adherence to the manual’s instructions, but users make mistakes. A single wrong keystroke shouldn’t cause a system crash, nor should inserting a wrong plug result in board damage. Therefore, various potential user errors must be predicted in advance and protected against.

• Common Mistake 9: The reason this board malfunctioned is due to issues with the other end’s board, not my responsibility.

  Correction: All external hardware interfaces should possess sufficient compatibility. Your system shouldn’t cease entirely just because the other end’s signal is abnormal. An abnormal signal should only affect the related functionalities, while other functions should continue working normally. It shouldn’t entirely cease functioning or incur permanent damage. Once the interface is restored, your system should promptly resume normal operation.

• Common Mistake 10: As long as the software is designed as required, this part of the circuit won’t have issues.

  Correction: Many hardware device characteristics are directly controlled by software, but software often encounters bugs. After a program malfunctions, it’s unpredictable how operations might proceed. Designers should ensure that regardless of the software’s actions, the hardware shouldn’t incur permanent damage in a short time frame.

Misconception 3: System Efficiency

• Common Mistake 11: Whether to use interrupts or polling for numerous tasks? Interrupts seem faster.

  Correction: Interrupts possess strong real-time capabilities but aren’t necessarily faster. If numerous interrupt tasks are stacking up, causing subsequent ones to follow rapidly, the system might crash in no time. If there’s a high number of tasks, especially frequent ones, the CPU expends substantial energy on interrupt overhead, significantly lowering system efficiency. Using polling might, in some cases, significantly enhance efficiency, but it might not meet real-time requirements. Hence, the best approach is to poll within interrupts, handling all accumulated tasks before exiting.

• Common Mistake 12: A CPU with a 100MHz clock can only handle 70%. Switching to a 200MHz clock will solve the issue.

  Correction: System processing capabilities involve various factors. In communication tasks, the bottleneck often lies in memory. No matter how fast the CPU is, if external access doesn’t speed up, it’s futile.

• Common Mistake 13: Using a larger CACHE for the CPU should make it faster.

  Correction: Increasing CACHE size doesn’t always enhance system performance. In some cases, turning off the CACHE might even be faster. This is because data in the CACHE must be repeatedly used to improve system efficiency. Generally, in communication systems, only instruction CACHE is typically open, and if data CACHE is activated, it’s restricted to specific storage spaces, such as stack portions. Additionally, program design must consider CACHE capacity and block size, involving critical code loop lengths and jump ranges. If a loop size nearly matches the CACHE, trouble arises when it repeatedly loops.

• Common Mistake 14: Memory interface timing should remain at the manufacturer’s default settings without modifications.

  Correction: BSP default values for memory interface settings are conservative. In practical use, they should be reasonably adjusted considering bus operating frequency and wait cycles. Sometimes, reducing the frequency can improve efficiency. For example, if the RAM access time is 70ns, with a bus frequency of 40MHz, setting it to 3 cycles, i.e., 75ns, is sufficient. However, at 50MHz bus frequency, it must be set to 4 cycles, extending the actual access time to 80ns.

• Common Mistake 15: This CPU has a DMA module, using it for data transfer will be faster.

  Correction: Genuine DMA involves hardware seizing the bus, simultaneously initiating both device ends, reading from one end, and writing to the other in one cycle. However, many embedded CPU DMAs are only simulated. Before each DMA transfer, substantial preparation (setting start address, length, etc.) is required. Often, data is first read into the chip’s internal storage before being written out, requiring two clock cycles for one data transfer, faster than software transfers (no instruction fetching, no loop jumps, etc.). But if transferring only a few bytes, involves a lot of setup and function calls, the efficiency isn’t high. Therefore, this kind of DMA is suitable only for large data blocks, avoiding blind usage.

• Common Mistake 16: If one CPU can’t handle it, using two distributed CPUs will double processing capabilities.

  Correction: For handling bricks, two people might be twice as efficient as one, but for painting, an additional person might hinder rather than help. Using multiple CPUs requires a substantial understanding of the business. It’s crucial to minimize the coordination cost between the CPUs, aiming for 1+1 to be as close to 2 as possible, but never less than 1.

Misconception 4: Low Power Design

• Common Mistake 17: Pulling up/down these bus signals with resistors feels reassuring.

  Correction: Not every signal needs pull-ups or pull-downs. Pulling a simple input signal with resistors results in a current of a few tens of microamps. However, pulling a driven signal could reach milliamps. Modern systems often have 32-bit addresses and data buses, along with signals post-244/245 isolation. If all are pulled up, several watts of power are consumed by these resistors (don’t treat these few watts with the notion of 80 cents per kilowatt-hour, reasons below).

• Common Mistake 18: Our system operates on a 220V supply, so power consumption isn’t a concern.

  Correction: Low-power design isn’t solely about saving electricity. It also reduces costs for power modules and cooling systems. Decreased current also minimizes electromagnetic radiation and thermal noise interference. Lower device temperatures correspondingly extend their lifespan (every 10-degree increase in semiconductor device operating temperature halves its lifespan). Power consumption should always be a consideration.

• Common Mistake 19: These small chips have low power consumption; no need to consider them.

  Correction: For internally less complex chips, determining power consumption is challenging. It’s mainly determined by the current on the pins. For instance, an ABT16244 consumes roughly less than 1mA without load, but it can drive a load of 60mA per pin (matching with tens of ohms resistors), resulting in a maximum power consumption of 60 * 16 = 960mA when fully loaded (however, this only accounts for the power supply current, with heat being dissipated by the load).

• Common Mistake 20: How should unused I/O ports on CPUs and FPGAs be handled? Can they be left idle for now?

  Correction: Leaving unused I/O ports floating could turn slight external disturbances into oscillating input signals. The power consumption of MOS devices is primarily determined by the number of gate circuit flips. If pulled up, each pin might have a microamp-level current. Therefore, it’s best to set them as outputs (while ensuring no other driven signals are connected).

• Common Mistake 21: This FPGA still has many unused gates; let’s use them all.

  Correction: An FPGA’s power consumption is directly proportional to the number of used flip-flops and their flip frequency. Hence, the power consumption of the same FPGA model may differ by a factor of 100 in different circuits at different times. Minimizing the number of high-speed flipping flip-flops is the fundamental method to reduce FPGA power consumption.

• Common Mistake 22: There are so many control signals for memory. Can we just ground the chip select line to speed up data output during read operations?

  Correction: For most memories, power consumption is over 100 times higher when chip select is active (regardless of OE and WE). Therefore, using CS to control chips as much as possible and minimizing the chip select pulse width while meeting other requirements is advisable.

• Common Mistake 23: Reducing power consumption is the responsibility of hardware personnel and is not related to software.

  Correction: Hardware sets the stage, but software runs the show. Almost every chip access and signal flip on the bus is controlled by software. Reducing external memory access (using more register variables, leveraging internal CACHE, etc.), timely responding to interrupts (often low-level active with pull-up resistors), and other specific measures for individual boards can significantly contribute to power reduction. For a successful board, both hardware and software must be managed.

• Common Mistake 24: Why are these signals overshooting? As long as they are well-matched, they’ll be eliminated.

  Correction: Except for a few specific signals (e.g., 100BASE-T, CML), overshooting is common. Not all overshooting requires matching, and even if matching is necessary, it doesn’t have to be perfect. TTL output impedance is less than 50 ohms, sometimes even 20 ohms. Using such large matching resistors results in a substantial current and unacceptable power consumption. Additionally, the signal amplitude might become too small. TTL, LVDS, 422, etc., signal matching should only ensure acceptable overshoot.

Misconception 5: Signal Integrity

• Common Mistake 25: These signals have been through simulation; surely, there are no issues.

  Correction: Simulation models can’t perfectly replicate physical components, let alone differences between various production batches. Real-world scenarios vary significantly, and simulations cannot exhaustively cover all possibilities, especially crosstalk. There was an incident where a specific length of data packets led to frequent packet loss. The issue was the length field value being 0xFF, causing interference with the adjacent WE signal on the bus, preventing RAM writes. Other data also caused interference with WE, albeit within acceptable limits. However, when the 8-bit bus concurrently switched between 0s and 1s, nearby signals couldn’t withstand the interference. The conclusion is that simulation results are for reference only and should leave a sufficient margin.

• Common Mistake 26: To ensure a clean power supply, the more decoupling capacitors, the better.

  Correction: In general, more decoupling capacitors result in a more stable power supply. However, having too many capacitors can lead to disadvantages such as increased costs, challenging wiring, and excessive inrush current during power-on. The key to decoupling capacitor design is selecting the right capacitance and proper placement. Chip manuals often provide reference designs for decoupling, which should be followed.

• Common Mistake 27: Since it’s a digital signal, sharper edges are undoubtedly better.

  Correction: Sharper edges result in a wider frequency spectrum and increased energy in high-frequency components. Higher frequency signals are more prone to radiation (e.g., microwave stations into mobile phones), thus easily interfering with other signals. Moreover, transmission quality on the wire deteriorates. Hence, whenever possible, use slower chips that match the signal speed.

• Common Mistake 28: Signal matching is quite troublesome. How to achieve good matching?

  Correction: Signal reflection becomes significant when the transmission time along the wire exceeds the signal’s rise time. Signal reflection occurs due to uneven line impedance. Signal matching aims to make the impedance at the driver end, load end, and transmission line similar. However, achieving good matching is also dependent on the PCB’s topology. Factors like a branch on the transmission line, a via, a corner, a connector, variations in distances to the ground plane, etc., can change impedance and complicate matching. Thus, for high-speed signals, employ point-to-point connections, minimizing vias, corners, etc.

• Common Mistake 29: A 100M data bus might be considered a high-frequency signal, but this clock signal is only 8K; it shouldn’t be an issue.

  Correction: Data bus values are typically sampled at the edge of a control or clock signal. As long as there’s enough setup and hold time around this edge, disturbances or overshoot beyond this range won’t have a significant impact (though it’s best to avoid overshoot beyond the maximum voltage the chip can handle). However, regardless of its frequency (which spans a wide spectrum), the edge of a clock signal is crucial. It must maintain monotonicity, and the rise/fall time needs to be within a certain range.