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Trench 3D NAND: The Future of Solid State Drives?

With previous hard drive technologies, 3D NAND will reach a point where it won't be able to meet high-density demands, & alternative tech will emerge.
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As with hard disk technology before it, 3D NAND will reach the point where it cannot meet the demand for high density, and alternative technologies will emerge. Semiconductor and nanotechnology research group IMEC believes the answer lies in the Trench 3D NAND.

The institute for the study of an article entitled “3 d NAND Flash and FeFET role in data storage roadmap” article discussed how NNAD units such as semiconductor devices in the x, y, and z dimensions (length, width, height) reduce the unit so that you can build on the wafer more intensive chips, to reduce costs or improve the equipment capacity.

Trench 3D NAND

Before introducing the Trench 3D NAND, let’s take a look at the 3D NAND. 3D NAND breaks the scaling down limits of flat NAND technology, which is based on floating (threshold voltages that change as cells write binary values and electrons flow through) gate transistors. Flat, or 2D, NAND cells shrink from 120nm, but from the 20 to 15nm level access speeds decrease, read error rates rise, and programming/erasing (write) cycles drop, all because there are not enough electrons available to keep the cell state stable.

3D NAND is flat elements flipped horizontally to vertically and connected in strings to form 3D layers. At the same time, the cell size was increased to 30-50nm with an X-Y spacing of 140nm, thus increasing the number of electrons per bit, making the cell easier and faster to read, and with longer life.

Schematic representation of a 3D-NAND Flash structure

NAND chip density (capacity) can be increased by increasing the number of layers, from 12 to 24, 32, 46, 96, 112, and now 144 and 176, depending on manufacturers, of course, who have even laid out a roadmap of 200+, 500+, or even 1000 layers.

3D NAND also increases density by adding bits to cells, from single-layer cells (SLC) to 2-bit double-layer cells (MLC), 3-bit three-layer cells (TLC), 4-bit four-layer cells (QLC), and 5-bit five-layer cells (PLC) under development.

The drawback to this approach is that each additional layer will prolong the production of the chip because etching 64 layers are easier than etching 112 and 144 layers, and the deeper the hole, the harder it is to keep etching.
As the number of layers increases, the casting tools needed to deposit layers of chemicals and etch holes must become more powerful and complex, increasing the cost. As the number of layers increases, there may also be stress-induced errors in the cell, requiring finer and more precise production controls.

But string stacking delays are inevitable, and at some point in the future, the additional production difficulties will make it too expensive to move to the next layer of technology. As a result, IMEC believes that NAND cells will have to become smaller again to be able to build denser chips that increase disk capacity or reduce power consumption and ease cooling.

In general, 3D NAND is designed with cylindrical ring grids (GAA). Shrinking cell size means a reduction in component layer thickness and height, which threatens the unit’s ability to meet performance, stability, and life requirements.

(Top) Gate-all-around vs. (Bottom) trench NAND Flash cell

IMEC researchers propose a groove-like architecture in which “the memory cells are no longer circular. They are implemented on the sidewalls of the groove, with two transistors at either end of the groove, which significantly increases bit density.

From an operational point of view, this grooved cell is similar to a flat cell (placed upright) compared to a circular GAA NAND flash cell,” they said.

In their opinion, “Although it has a slight loss in electrical characteristics (e.g., programming/erasing), the cell area in a trench-like configuration can be reduced in the x-y direction compared to GAA. Therefore, trench cells are proposed as the next-generation NAND Flash cell architecture, which is expected to reduce the x-y pitch from today’s 140nm to 30nm.

And the reduction of the z-dimension (height) may require significant changes. “The z-shrink of the NAND Flash layer stack involves extruding the materials used to create the word line layer, including the word line metal,” said IMEC.

A lesser thickness of word line metal introduces an unwanted increase in resistivity, which increases resistive-capacitive (RC) latency and slows access times,” IMEC said. Therefore, IMEC is looking for alternative metals such as Ru (ruthenium) and Mo (molybdenum), which may have lower resistivity at smaller sizes.”

IMEC researchers are “exploring alternative materials for charge trap layers, tunneling dielectrics, and metal gate stacks and studying their impact on memory performance.”

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DiskMFR Field Sales Manager - Leo

It’s Leo Zhi. He was born on August 1987. Major in Electronic Engineering & Business English, He is an Enthusiastic professional, a responsible person, and computer hardware & software literate. Proficient in NAND flash products for more than 10 years, critical thinking skills, outstanding leadership, excellent Teamwork, and interpersonal skills.  Understanding customer technical queries and issues, providing initial analysis and solutions. If you have any queries, Please feel free to let me know, Thanks

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