Nowadays, high-end computing chips are becoming increasingly large, and TSMC is exploring various ways to cope with this. They are now deeply advancing CoWoS packaging technology, claiming to be able to create giant chips nearly 8000 square millimeters in size, with a power consumption of 1000W, and a performance up to 40 times higher than that of standard processors.
Currently, the largest intermediary layer area of TSMC’s CoWoS packaging chips can reach 2831 square millimeters, about 3.3 times the limit of TSMC’s photomask size—EUV extreme ultraviolet photolithography can achieve a maximum photomask size of 858 square millimeters, and TSMC uses a 830 square millimeter mask.
Chips like NVIDIA’s B200 and AMD’s MI300X use this packaging to integrate large computing modules with multiple HBM memory chips.
Next year, or a little later, TSMC will launch the next-generation CoWoS-L packaging technology, with an intermediary layer area of up to 4719 square millimeters, about 5.5 times the photomask limit, requiring a large 10000 square millimeter (100×100 mm) substrate.
It can integrate up to 12 HBM memory chips, including the next-generation HBM4.
But that’s not all. TSMC also plans to further increase the intermediary layer to 7885 square millimeters, about 9.5 times the photomask limit, requiring an 18000 square millimeter substrate, thus packaging up to 4 computing chips, 12 HBM memory chips, and other IPs.
This already exceeds the size of a standard CD case (typically 142×125 mm)!
Still not finished, TSMC is continuing to research SoW-X wafer-level packaging technology, currently used only by Cerebras and Tesla.
Such giant chips not only require complex packaging technology but also bring challenges of high power consumption and heat generation, with TSMC estimating a power consumption level of 1000W.
To address this, TSMC plans to integrate a complete power management IC into the RDL intermediary layer within the CoWoS-L packaging, thus shortening the power supply distance, reducing the number of active ICs, lowering parasitic resistance, and improving system-level power efficiency.
This power management IC will be manufactured using TSMC’s N16 process and TSV (through-silicon via) technology.
For heat dissipation, direct contact liquid cooling and immersion liquid cooling must be considered.
Additionally, the OAM 2.0 module shape measures 102×165 mm, and the 100×100 mm substrate is already close to the limit; anything larger, such as 120×150 mm, would exceed the limit, thus requiring the industry to establish new OAM form standards.
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