When it comes to high speed, the majority of the reaction is grain quality and transmission protocol, in the vast and calculating flow in the future, as long as involving logic operation ability and real-time access to information and make decisions, will think of "high speed", "CPU", "NAND", "DRAM" keyword, in the era of big data, these a few keywords represent the core, But today's post introduces you to transistor technology.
Development of transistors
From the CMOS technology point of view, in addition to the general logic and power device products, there is also NOR flash technology. For DRAM, NAND, and logic products below 25nm, their transistors have been developed into surround gate transistors (SGT), surround gate transistors (GAA, GAAFET), and fin-type field-effect transistors (FinFET) respectively.
Recent developments in mainstream transistors and product applications
3D NAND FLASH under 1 Xnm is composed of vertical current GAA memory. The circuit logic of FinFET has gradually evolved from CMOS to 2d enhanced structure, which is in parallel with multi-fins or MBCFET to increase the current size. All the above technologies require more advanced phytoliths to complete. Such as deep ultraviolet DUV or extreme ultraviolet EUV.
Improvements in storage node technology and density depend on two key technologies: emerging materials and innovative structures. Memory derived from emerging materials (such as FRAM, MRAM, PRAM, and RRAM) has been manufactured and used by a small number of manufacturers.
Limitations of GAA
Observing the major differences between the four storage units (the GAA process is omitted here), the GAA unit split manufacturing model used by the first three companies is based on the GAA process. After changing from a GAA unit to an oval, it is technically Split into a Split GAA unit.
Comparison of main characteristics of 3D-NAND flash cell formation
The four companies above share similarities, including vertical current, multi-layer stacking technology, and ways of connecting single wires, bit wires, and word wires. Seemingly similar in appearance, the structure of the current operating area of Hexas memory is significantly different from the previous three.
In order to perform the processing of the storage unit module, the first three units must be fixed to certain values for subsequent processing. The diameter of the bubble is one of the short axes of the Split GAA bubble and will affect the final density. However, the FanFET storage unit module does not have such problems in process integration, because the FanFET storage unit’s cell shape and feature size can be freely adjusted according to the developer’s needs, and density can be effectively changed. The characteristic size of the three companies mentioned above is about 3.5F 2 ~ 6F 2, because the cell itself is a closed-loop structure, and the isolation layer between the cells must comply with the design rules.
In addition, due to the sequence and difference of various processes, such as pre-grid and post-grid processes, the series of isolation layers and cells, as well as film residues and CD bias on the process flow, may result in varying degrees of marginal effects.
The serious problem with splitting the GAA is that it is a closed-loop structure in a unit, and this structure may limit the size of the unit. When the cell shrinks, it faces the problem of filling dielectric film and BL. At the same time, splitting GAA cells increases the size of features, resulting in a decrease in memory density per unit area.
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