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What exactly is memory timing? Outsiders see frequency, insiders see timing?

When buying memory for the computer, most people can notice the capacity that sees memory and frequency parameters, generally speaking, capacity is better with greater, and frequency is better with higher.  Of course, these two parameters are important, but there is another important parameter that is often overlooked: memory timing.  So what is RAM timing, and how does it affect memory performance?  DiskMFR takes a look at this RAM parameter.

Timing affects the latency between various common operations on a memory chip. If the latency exceeds a certain limit, the performance of memory will be affected.  In a nutshell, the timing of memory is a description of the inherent delay that an internal entity may experience when performing its various operations. 

RAM timing is measured in clock cycles. You may see a string of numbers separated by dashes on the product page of a memory stick, such as 16-18-18-38, and these numbers are called memory timings. Essentially, since they represent latency, the lower the timings, the better. These four numbers represent the so-called “primary timing” and have the most significant impact on latency.

The parameters corresponding to the four numbers of memory timing are CL, tRCD, tRP, and tRAS, all in units of time cycles. Among them, CL (CAS Latency) indicates “delay time of column address access, which is the most important parameter in timing”; tRCD (RAS to CAS Delay) indicates “delay time of memory row address transfer to column address”; tRP (RAS Precharge Time) indicates “precharge time of memory row address select pulse”; tRAS (RAS Active Time) denotes “the time when the row address is active”.

After reading the above, are you more confused? Don’t worry, let’s take a simple example to talk about it.

We can imagine the memory storing data as a grid, and each square stores different data, and the CPU issues the corresponding instruction to the memory for whatever data it needs.

  • For example, the CPU wants the data in location C3. After the memory receives the instruction from the CPU, it has to determine exactly which line the data is in first. The second parameter of the timing, tRCD, represents this time, meaning how long the memory controller has to wait to access the line after receiving the instruction from the line.
  • Once RAM determines which row the data is in, to find the data, it must also determine the column.  The first number in the sequence, CL, indicates how long memory must wait to access a specific column after determining the number of rows. 

After determining the number of rows and columns, the target data can be found accurately, so CL is an exact value and any changes will affect the location of the target data, so it is one of the most critical parameters in the timing and plays a pivotal role in the memory performance.

The third parameter of RAM timing, tRP, is the time required to wait for another row after one has been determined.

The fourth parameter, tRAS, can be simply understood as a time for memory to write or read data, and it is generally close to the sum of the first three parameters.

Therefore, the lower the memory timings the better, provided that stability is guaranteed. However, we know that many memory sticks are now able to overclock, and high frequency and low timing contradict each other, generally frequency up, timing will have to be sacrificed, in order to low enough timing, frequency and difficult to pull up. For example, in the DDR5 memory released by major storage manufacturers this year, the frequency did go up, but the timing is also relatively DDR4 memory a lot higher.

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